Tail merging can convert an undef use into a normal one when creating a
common tail. Doing so can make the register live out from a block which
previously contained the undef use. To keep the liveness up-to-date,
insert IMPLICIT_DEFs in such blocks when necessary.
To enable this patch the computeLiveIns() function which used to
compute live-ins for a block and set them immediately is split into new
functions:
- computeLiveIns() just computes the live-ins in a LivePhysRegs set.
- addLiveIns() applies the live-ins to a block live-in list.
- computeAndAddLiveIns() is a convenience function combining the other
two functions and behaving like computeLiveIns() before this patch.
Based on a patch by Krzysztof Parzyszek <kparzysz@codeaurora.org>
Differential Revision: https://reviews.llvm.org/D37034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312668 91177308-0d34-0410-b5e6-96231b3b80d8
When if-converting a diamond, two separate blocks will be placed back
to back to form a straight line code. To ensure correctness of the
liveness information, any registers that are live in the second block
should not be killed in the first block, even if they were in the
original code.
Additionally, when the two blocks share common instructions at the
beginning, these instructions will not be duplicated, but only placed
once, before both of the blocks. Since the function "isIdenticalTo"
(as used here) ignores kill flags, the common initial code in one
block may have a kill flag for a register that is live in the other
block.
Because the code that removes kill flags only runs for the non-common
parts of the predicated blocks, a kill flag mismatch in the common
code could still lead to a live register being killed prematurely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312654 91177308-0d34-0410-b5e6-96231b3b80d8
The check (assuming positive stride) for validity of memmove should be
(a) the destination is at a lower address than the source, or
(b) the distance between the source and destination is greater than or
equal the number of bytes copied.
For the second part it is sufficient to assume that the destination
is at a higher address, since the opposite case is covered by (a).
The distance calculation was previously done by subtracting the
pointers in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311650 91177308-0d34-0410-b5e6-96231b3b80d8
isLegalAddressingMode() has recently gained the extra optional Instruction*
parameter, and therefore it can now do the job that previously only
isFoldableMemAccess() could do.
The SystemZ implementation of isLegalAddressingMode() has gained the
functionality of checking for offsets, which used to be done with
isFoldableMemAccess().
The isFoldableMemAccess() hook has been removed everywhere.
Review: Quentin Colombet, Ulrich Weigand
https://reviews.llvm.org/D35933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310463 91177308-0d34-0410-b5e6-96231b3b80d8
Certain operations require vector of i1 values. However, for Hexagon
architecture compatibility, they need to be represented as vector of i8.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309677 91177308-0d34-0410-b5e6-96231b3b80d8
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308186 91177308-0d34-0410-b5e6-96231b3b80d8
This is the LLVM part, adding definitions for
void @llvm.hexagon.Y2.dccleana(i8*)
void @llvm.hexagon.Y2.dccleaninva(i8*)
void @llvm.hexagon.Y2.dcinva(i8*)
void @llvm.hexagon.Y2.dczeroa(i8*)
void @llvm.hexagon.Y4.l2fetch(i8*, i32)
void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308032 91177308-0d34-0410-b5e6-96231b3b80d8
Account for the fact that both, the feeder and the compare can be moved
over instructions that kill registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306443 91177308-0d34-0410-b5e6-96231b3b80d8
The feeder instruction will be moved to right before the compare, so
the updating code should not be looking for kills past the compare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306059 91177308-0d34-0410-b5e6-96231b3b80d8
Reserve an extra scavenging stack slot if the offset field in store-
-immediate instructions may overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306004 91177308-0d34-0410-b5e6-96231b3b80d8
The second part of r305300: when placing the mux at the later location,
make sure that it won't use any register that was killed between the
two original instructions. Remove any such kills and transfer them to
the mux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305553 91177308-0d34-0410-b5e6-96231b3b80d8
Store-immediate instructions have a non-extendable offset. Since the
actual offset for a stack object is not known until much later, only
generate these stores when the stack size (at the time of instruction
selection) is small.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305305 91177308-0d34-0410-b5e6-96231b3b80d8
When a mux instruction is created from a pair of complementary conditional
transfers, it can be placed at the location of either the earlier or the
later of the transfers. Since it will use the operands of the original
transfers, putting it in the earlier location may hoist a kill of a source
register that was originally further down. Make sure the kill flag is
removed if the register is still used afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305300 91177308-0d34-0410-b5e6-96231b3b80d8
The conversion of shifts from right shifts to left shifts may fail.
In such case, the pmpy recognition cannot proceed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305289 91177308-0d34-0410-b5e6-96231b3b80d8
An incorrect check in the packetizer lead to an attempt to convert
an unconditional branch to a .new (conditional) form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304442 91177308-0d34-0410-b5e6-96231b3b80d8
The initial assumption was that the simplification would converge to a
fixed point relatvely quickly. Turns out that there are legitimate situa-
tions where the complexity of the code causes it to take a large number
of iterations.
Two main changes:
- Instead of aborting upon hitting the limit, simply return nullptr.
- Reduce the limit to 10,000 from 100,000.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304441 91177308-0d34-0410-b5e6-96231b3b80d8
For multiplications of 64-bit values (giving 64-bit result), detect
cases where the arguments are sign-extended 32-bit values, on a per-
operand basis. This will allow few patterns to match a wider variety
of combinations in which extensions can occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304223 91177308-0d34-0410-b5e6-96231b3b80d8
Rewrite fixupKills() to use the LivePhysRegs class. Simplifies the code
and fixes a bug where the CSR registers in return blocks where missed
leading to invalid kill flags. Also remove the unnecessary rule that we
wouldn't set kill flags on tied operands.
No tests as I have an upcoming commit improving MachineVerifier checks
to catch these cases in multiple existing lit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304055 91177308-0d34-0410-b5e6-96231b3b80d8
Krzysztof Parzyszek