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9 Commits

Author SHA1 Message Date
Craig Topper 3662f50ee1 [AVX512] Add 128->256 vbroadcastf64x2/vbroadcasti64x2 instructions to the EVEX->VEX table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311307 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-21 05:03:28 +00:00
Benjamin Kramer 01a5eed38e Another instance where GCC doesn't understand implicit construction of StringLiteral. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298703 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-24 14:17:56 +00:00
Benjamin Kramer 1dd3d84b80 Make GCC happy again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298702 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-24 14:15:35 +00:00
Benjamin Kramer 54c10c042d Don't build up std::vectors with constant sizes when an array suffices. 
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298701 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-24 14:11:47 +00:00
Craig Topper 760a31890d Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead." 
This reverts r297596.

There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297602 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-13 05:34:03 +00:00
Craig Topper c68171ad8f [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead. 
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-13 00:36:49 +00:00
Craig Topper 026472f7e8 [X86] Minor formatting tweaks in EVEX to VEX tables. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297595 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-13 00:36:46 +00:00
Ayman Musa 69112bd6d2 [X86] Quick fix for build bot failure (r297127) due to unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297130 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-07 08:56:27 +00:00
Ayman Musa b59d8041db [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables. 
X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible.
It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals.
This TableGen backend replaces the tables by automatically generating them.

Differential Revision: https://reviews.llvm.org/D30451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297127 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-07 08:11:19 +00:00