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78 Commits

Author SHA1 Message Date
Matt Arsenault
c7d2de0c8f AMDGPU/GlobalISel: Select private loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366248 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-16 19:22:21 +00:00
Matt Arsenault
329f885366 AMDGPU/GlobalISel: Select flat stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366246 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-16 18:42:53 +00:00
Matt Arsenault
b18edea81b AMDGPU/GlobalISel: Select flat loads 
Now that the patterns use the new PatFrag address space support, the
only blocker to importing most load patterns is the addressing mode
complex patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366237 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-16 18:05:29 +00:00
Matt Arsenault
aeefee98c1 AMDGPU/GlobalISel: Fix test failures in release build 
Apparently the check for legal instructions during instruction
select does not happen without an asserts build, so these would
successfully select in release, and fail in debug.

Make s16 and/or/xor legal. These can just be selected directly
to the 32-bit operation, as is already done in SelectionDAG, so just
make them legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366210 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-16 14:28:30 +00:00
Matt Arsenault
46513b57db AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366121 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:50:07 +00:00
Matt Arsenault
848db45c88 AMDGPU/GlobalISel: Don't constrain source register of VCC copies 
This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366120 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:48:36 +00:00
Matt Arsenault
fcd8db8a7d AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies 
The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366119 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:46:48 +00:00
Matt Arsenault
0cf596c83a AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366118 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:45:49 +00:00
Matt Arsenault
0774fb325e AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC 
This was emitting a copy from a 32-bit register to a 64-bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366117 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:44:07 +00:00
Matt Arsenault
2e692a0fec AMDGPU/GlobalISel: Fix G_ICMP for wave32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366114 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 19:39:31 +00:00
Matt Arsenault
92d1538833 AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366102 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 18:25:24 +00:00
Matt Arsenault
9aa5131c1d AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366099 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 18:18:46 +00:00
Matt Arsenault
227403b223 AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366087 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-15 17:26:43 +00:00
Matt Arsenault
cd159ec3d2 AMDGPU/GlobalISel: Select G_SUB 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365484 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-09 14:05:11 +00:00
Matt Arsenault
583f33b170 AMDGPU/GlobalISel: Select G_UNMERGE_VALUES 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365483 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-09 14:02:26 +00:00
Matt Arsenault
fd0d82251d AMDGPU/GlobalISel: Select G_MERGE_VALUES 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365482 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-09 14:02:20 +00:00
Matt Arsenault
5955c03166 AMDGPU/GlobalISel: Try generated matcher with intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364933 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-02 14:52:16 +00:00
Matt Arsenault
59c422424e AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands 
The register bank for the destination of the sample argument copy was
wrong. We shouldn't be constraining each source to the result register
bank. Allow constraining the original register to the right size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364928 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-02 14:40:22 +00:00
Matt Arsenault
0368e15ad1 AMDGPU/GlobalISel: Select G_FENCE 
Manually select to workaround tablegen emitter emitting checks for
G_CONSTANT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364927 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-02 14:17:38 +00:00
Matt Arsenault
51744f169f AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364835 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 18:49:01 +00:00
Matt Arsenault
87f9f81250 AMDGPU/GlobalISel: Fail instead of assert when selecting loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364807 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 16:36:39 +00:00
Matt Arsenault
5060182440 AMDGPU/GlobalISel: Complete implementation of G_GEP 
Also works around tablegen defect in selecting add with unused carry,
but if we have to manually select GEP, might as well handle add
manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364806 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 16:34:48 +00:00
Matt Arsenault
b1c22290af AMDGPU/GlobalISel: Select G_PHI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364805 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 16:32:47 +00:00
Tom Stellard
962c2a67ea AMDGPU/GlobalISel: Implement select for 32-bit G_ADD 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364797 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 16:09:33 +00:00
Matt Arsenault
ebb2f49e2d AMDGPU/GlobalISel: Select G_BRCOND for vcc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364795 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 16:06:02 +00:00
Matt Arsenault
23031b8243 AMDGPU/GlobalISel: Select G_FRAME_INDEX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364789 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 15:48:18 +00:00
Matt Arsenault
faac328d81 AMDGPU/GlobalISel: Make s16 select legal 
This is easy to handle and avoids legalization artifacts which are
likely to obscure combines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364787 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 15:42:47 +00:00
Matt Arsenault
1adfb58fa1 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364786 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 15:39:27 +00:00
Matt Arsenault
d3f47bd68b AMDGPU/GlobalISel: Tolerate copies with no type set 
isVCC has the same bug, but isn't used in a context where it can cause
a problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364784 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 15:23:04 +00:00
Matt Arsenault
f0431d4012 AMDGPU/GlobalISel: Select src modifiers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364782 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 15:18:56 +00:00
Matt Arsenault
d12e3c69f0 AMDGPU/GlobalISel: Fail on store to 32-bit address space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364766 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 13:37:39 +00:00
Matt Arsenault
cd8d93f169 AMDGPU/GlobalISel: Improve icmp selection coverage. 
Select s64 eq/ne scalar icmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364765 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 13:34:26 +00:00
Matt Arsenault
23b47db4b0 AMDGPU/GlobalISel: Fix scc->vcc copy handling 
This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.

Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364761 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 13:22:07 +00:00
Matt Arsenault
bc712eaf90 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate 
Zext from s1 is the only case where this should do anything with the
current legal extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364760 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-01 13:22:06 +00:00
Matt Arsenault
e3c60dfc18 AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364308 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-25 13:18:11 +00:00
Matt Arsenault
d73371c16b AMDGPU/GlobalISel: Select G_TRUNC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364215 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-24 18:02:18 +00:00
Matt Arsenault
2ca6872584 AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1 
Try to fail for scc, since I don't think that should ever be produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364199 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-24 16:24:03 +00:00
Matt Arsenault
33482eea4c AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic ID 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363578 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-17 17:01:27 +00:00
Tom Stellard
2d928b87de AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT 
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363576 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-17 16:27:43 +00:00
Stanislav Mekhanoshin
0b378026ac [AMDGPU] gfx1010 VMEM and SMEM implementation 
Differential Revision: https://reviews.llvm.org/D61330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359621 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-04-30 22:08:23 +00:00
Tom Stellard
44c4c1d525 AMDGPU/GlobalISel: Implement select for G_INSERT 
Re-commit r344310.

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D53116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355159 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-03-01 00:50:26 +00:00
Tom Stellard
568bf88e60 AMDGPU/GlobalISel: Implement select for G_EXTRACT 
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49714

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355156 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-02-28 23:37:48 +00:00
Tom Stellard
21d7b5a1d6 AMDGPU/GlobalISel: Move SMRD selection logic to TableGen 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52922

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354516 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-02-20 21:02:37 +00:00
Chandler Carruth
6b547686c5 Update the file headers across all of the LLVM projects in the monorepo 
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-01-19 08:50:56 +00:00
Tom Stellard
639949cb15 Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 
This reverts commit r344310.

The test case was failing on some bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344317 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-11 23:36:46 +00:00
Tom Stellard
1a0ffaa454 AMDGPU/GlobalISel: Implement select for G_INSERT 
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D53116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344310 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-11 22:49:54 +00:00
Tom Stellard
69f718971f AMDGPU/GlobalISel: Add support for G_INTTOPTR 
Summary: This is a no-op.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343839 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-05 04:34:09 +00:00
Matt Arsenault
7e212e4168 AMDGPU: Remove remnants of old address space mapping 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341165 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-08-31 05:49:54 +00:00
Tom Stellard
37f081b80d AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D46172

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337056 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-07-13 22:16:03 +00:00
Tom Stellard
504eed44cd AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45882

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337046 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-07-13 21:05:14 +00:00