Histogram entries are now ordered by key. This should improves their
readability when statistics are printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334961 91177308-0d34-0410-b5e6-96231b3b80d8
When the destination register of a XOP instruction is an XMM register, bits
[255:128] of the corresponding YMM register are cleared.
When the destination register of a EVEX encoded instruction is an XMM/YMM
register, the upper bits of the corresponding ZMM are cleared.
On processors that feature AVX512, a write to an XMM registers always clears the
upper portion of the corresponding ZMM register if the instruction is VEX or
EVEX encoded.
These new tests show some interesting cases which aren't correctly analyzed by
llvm-mca. The lack of knowledge related to the implicit update on the
super-registers is addressed by D48225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334945 91177308-0d34-0410-b5e6-96231b3b80d8
There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334907 91177308-0d34-0410-b5e6-96231b3b80d8
Added a Generic x86 cpu set of resource tests to allow us to check all ISAs.
We currently use SandyBridge as our generic CPU model, but it's better if we actually duplicate these tests for if/when we change the model, it also means we don't end up polluting the SandyBridge folder with tests for ISAs it doesn't support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334853 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
While that is indeed a quite interesting summary stat,
there are cases where it does not really add anything
other than consuming extra lines.
Declutters the output of D48190.
Reviewers: RKSimon, andreadb, courbet, craig.topper
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334833 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
There does not seem to be any other tests for this.
Split off from D47676.
Reviewers: RKSimon, craig.topper, courbet, andreadb
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334832 91177308-0d34-0410-b5e6-96231b3b80d8
On x86-64, a write to register EAX implicitly clears the upper half or RAX.
128-bit AVX instructions clear the upper 128-bit of the YMM register that
aliases the XMM definition register.
llvm-mca doesn't know about register writes that implicitly clear the upper
portion of an aliasing super-register. This issue will be fixed in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334742 91177308-0d34-0410-b5e6-96231b3b80d8
This test checks that a physical register is correctly allocated for the partial
write to register BX.
The ADD instruction has to wait for the write to RBX (and BX) before being
executed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334730 91177308-0d34-0410-b5e6-96231b3b80d8
Fixes PR37790.
In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a
load (or store) as "ready to execute" effectively bypassing older memory barrier
instructions.
To reproduce this bug, the memory barrier must be the first instruction in the
input assembly sequence, and it doesn't have to perform any register writes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334633 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This fixes most of the scheduling info for SKX vector operations.
I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM.
The before/after llvm-exegesis analysis are in the phabricator diff.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334407 91177308-0d34-0410-b5e6-96231b3b80d8
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), these instructions are dependency breaking and fast-path zero the destination register (and appropriate EFLAGS bits).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334303 91177308-0d34-0410-b5e6-96231b3b80d8
Reduces output size and we're only wanting to check that the instructions are fast-path'd (just Dispatch+Retire) anyhow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334292 91177308-0d34-0410-b5e6-96231b3b80d8
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334119 91177308-0d34-0410-b5e6-96231b3b80d8
I noticed while working on zero-idiom + dependency-breaking support (PR36671) that most of our binary instruction tests were reusing the same src registers, which would cause the tests to fail once we enable scalar zero-idiom support on btver2. Fixed in all targets to keep them in sync.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334110 91177308-0d34-0410-b5e6-96231b3b80d8
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.
TODO: Scalar instructions still need to be tested (need to check EFLAGS handling).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334104 91177308-0d34-0410-b5e6-96231b3b80d8
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.
Added extra code comments in class ReadState to better describe each field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334028 91177308-0d34-0410-b5e6-96231b3b80d8
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html
This fixes PR36672.
The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes. This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).
Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
1) a change that teaches llvm-mca how to resolve variant scheduling classes.
2) a change to the BtVer2 scheduling model that allows us to special-case
packed XOR zero-idioms (this partially fixes PR36671).
Differential Revision: https://reviews.llvm.org/D47374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333909 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
It's super irritating.
[properly configured] git client then complains about that double-newline,
and you have to use `--force` to ignore the warning, since even if you
fix it manually, it will be reintroduced the very next runtime :/
Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell
Reviewed By: gbedwell
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333887 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
{FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded.
- I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
- For ZnVer1 and Atom, values were transferred form InstRWs.
- For SLM and BtVer2, I've guessed some values :(
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333656 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
- I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
- For ZnVer1 and Atom, values were transferred form `InstRW`s.
- For SLM and BtVer2, values are from Agner.
This is split off from https://reviews.llvm.org/D47377
Reviewers: RKSimon, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333642 91177308-0d34-0410-b5e6-96231b3b80d8
As confirmed by llvm-exegesis, there is no scheduler difference between MOVDQA/MOVDQU and VMOVDQA/VMOVDQU xmm reg-reg moves
Another chapter in the never ending crusade to remove useless InstRW overrides from the x86 scheduler models......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333271 91177308-0d34-0410-b5e6-96231b3b80d8
Previously update_mca_test_checks worked entirely at "block" level where
a block is some sequence of lines delimited by at least one empty line.
This generally worked well, but could sometimes lead to excessive
repetition of check lines for various prefixes if some block was almost
identical between prefixes, but not quite (for example, due to a
different dispatch width in the otherwise identical summary views).
This new analyis attempts to split blocks further in the case where the
following conditions are met:
a) There is some prefix common to every RUN line (typically 'ALL').
b) The first line of the block is common to the output with every prefix.
c) The block has the same number of lines for the output with every prefix.
Also, regenerated all llvm-mca test files with the following command:
update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s"
The new analysis showed a "multiple lines not disambiguated by prefixes" warning
for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some
explicit prefixes to each of the RUN lines in that test.
Differential Revision: https://reviews.llvm.org/D47321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333204 91177308-0d34-0410-b5e6-96231b3b80d8
This patch implements the "block reciprocal throughput" computation in the
SummaryView.
The block reciprocal throughput is computed as the MAX of:
- NumMicroOps / DispatchWidth
- Resource Cycles / #Units (for every resource consumed).
The block throughput is bounded from above by the hardware dispatch throughput.
That is because the DispatchWidth is an upper bound on how many opcodes can be part
of a single dispatch group.
The block throughput is also limited by the amount of hardware parallelism. The
number of available resource units affects how the resource pressure is
distributed, and also how many blocks can be delivered every cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333095 91177308-0d34-0410-b5e6-96231b3b80d8
This is to keep the Jaguar model's naming convention. Processor resources all
have a 'J' prefix in the BtVer2 scheduling model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332851 91177308-0d34-0410-b5e6-96231b3b80d8
BtVer2 - fix NumMicroOp and account for the Lat+6cy GPR->XMM and Lat+1cy XMm->GPR delays (see rL332737)
The high number of MOVD/MOVQ equivalent instructions meant that there were a number of missed patterns in SNB/Znver1:
SNB - add missing GPR<->MMX costs (taken from Agner / Intel AOM)
Znver1 - add missing GPR<->XMM MOVQ costs (taken from Agner)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332745 91177308-0d34-0410-b5e6-96231b3b80d8
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.
Fixes BtVer2/SLM which have different behaviours for GPR stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332718 91177308-0d34-0410-b5e6-96231b3b80d8
Retag some instructions that were missed when we split off vector load/store/moves - MOVSS/MOVSD/MOVHPD/MOVHPD/MOVLPD/MOVLPS etc.
Fixes BtVer2/SLM which have different behaviours for GPR stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332714 91177308-0d34-0410-b5e6-96231b3b80d8
Flag -all-views enables all the views.
Flag -all-stats enables all the views that print hardware statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332602 91177308-0d34-0410-b5e6-96231b3b80d8
BtVer2 - Fixes schedules for (V)CVTPS2PD instructions
A lot of the Intel models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332376 91177308-0d34-0410-b5e6-96231b3b80d8
Btver2 - VCVTPH2PSYrm needs to double pump the AGU
Broadwell - missing VCVTPS2PH*mr stores extra latency
Allows us to remove the WriteCvtF2FSt conversion store class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332357 91177308-0d34-0410-b5e6-96231b3b80d8
Roman Lebedev