18 Commits

Author SHA1 Message Date
Andrea Di Biagio
47acfadfe7 [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

This fixes PR36672.

The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes.  This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).

Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
 1) a change that teaches llvm-mca how to resolve variant scheduling classes.
 2) a change to the BtVer2 scheduling model that allows us to special-case
    packed XOR zero-idioms (this partially fixes PR36671).

Differential Revision: https://reviews.llvm.org/D47374 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333909 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 15:43:09 +00:00
Andrea Di Biagio
b29b4919ea [llvm-mca] Track cycles contributed by resources that are in a 'Super' relationship.
This is required if we want to correctly match the behavior of method
SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set of
"consumed" processor resources and resource cycles, the logic in
ExpandProcResource() doesn't update the number of resource cycles contributed by
a "Super" resource to a group.  We need to take this into account when a model
declares a processor resource which is part of a 'processor resource group', and
it is also used as the "Super" of other resources.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333892 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 12:23:07 +00:00
Nicola Zaghen
0818e789cb Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.

In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.

Differential Revision: https://reviews.llvm.org/D43624



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332240 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 12:53:11 +00:00
Andrea Di Biagio
f6d466f5ba [llvm-mca] use colors for warnings and notes generated by InstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331517 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-04 13:52:12 +00:00
Andrea Di Biagio
f501530ff6 [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.
We don't need to pass the instruction index to the method that constructs new
instruction descriptors.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331516 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-04 13:10:10 +00:00
Andrea Di Biagio
8155479799 [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330807 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:38:58 +00:00
Andrea Di Biagio
e509ab0cbd [llvm-mca] Do not assume that implicit reads cannot be associated with ReadAdvance entries.
Before, the instruction builder incorrectly assumed that only explicit reads
could have been associated with ReadAdvance entries.
This patch fixes the issue and adds a test to verify it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328972 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-02 13:46:49 +00:00
Mandeep Singh Grang
4ead3eb171 [tools] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: JDevlieghere, zturner, echristo, dberris, friss

Reviewed By: echristo

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D45141

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328943 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-01 21:24:53 +00:00
Andrea Di Biagio
8ff27dbe39 [llvm-mca] Correctly set the ReadAdvance information for register use operands.
The tool was passing the wrong operand index to method
MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and
not the operand index. This was found when testing X86 code where instructions
had a memory folded operand.

This patch fixes the issue and adds test read-advance-1.s to ensure that
the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328790 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-29 14:26:56 +00:00
Andrea Di Biagio
add7b3e24e [llvm-mca] run clang-format on all files.
This also addresses Simon's review comment in D44839.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328428 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-24 16:05:36 +00:00
Andrea Di Biagio
280f00a153 [llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328187 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-22 10:19:20 +00:00
Andrea Di Biagio
0183d4fd60 [llvm-mca] Remove const from a bunch of ArrayRef. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328018 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 19:06:34 +00:00
Andrea Di Biagio
0d055e19c3 [llvm-mca] Use llvm::make_unique in a few places. NFC
Also, clang-format a couple of DEBUG functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327978 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 12:58:34 +00:00
Andrea Di Biagio
bce5921b79 [llvm-mca] Move the routine that computes processor resource masks to its own file.
Function computeProcResourceMasks is used by the ResourceManager (owned by the
Scheduler) to compute resource masks for processor resources.  Before this
refactoring, there was an implicit dependency between the Scheduler and the
InstrBuilder. That is because InstrBuilder has to know about resource masks when
computing the set of processor resources consumed by a new instruction.

With this patch, the functionality that computes resource masks has been
extracted from the ResourceManager, and moved to a separate file (Support.h). 
This helps removing the dependency between the Scheduler and the InstrBuilder.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327973 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 12:25:54 +00:00
Andrea Di Biagio
ce305b3012 [llvm-mca] Remove unused variable from InstrBuilder.cpp. NFC
This was causing a buildbot failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327517 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-14 15:19:47 +00:00
Andrea Di Biagio
2a50eccea8 [llvm-mca] Move the logic that updates the register files from InstrBuilder to DispatchUnit. NFCI
Before this patch, the register file was always updated at instruction creation
time. That means, new read-after-write dependencies, and new temporary registers
were allocated at instruction creation time.

This patch refactors the code in InstrBuilder, and move all the logic that
updates the register file into the dispatch unit. We only want to update the
register file when instructions are effectively dispatched (not before).

This refactoring also helps removing a bad dependency between the InstrBuilder
and the DispatchUnit.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327514 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-14 14:57:23 +00:00
Andrea Di Biagio
604cc1c689 [llvm-mca] Simplify code that computes the latency of an instruction in
InstrBuilder. NFCI

This was possible because of r327406, which added function`computeInstrLatency`
to MCSchedModel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327415 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-13 15:59:59 +00:00
Andrea Di Biagio
29b29cc6a9 [llvm-mca] LLVM Machine Code Analyzer.
llvm-mca is an LLVM based performance analysis tool that can be used to
statically measure the performance of code, and to help triage potential
problems with target scheduling models.

llvm-mca uses information which is already available in LLVM (e.g. scheduling
models) to statically measure the performance of machine code in a specific cpu.
Performance is measured in terms of throughput as well as processor resource
consumption. The tool currently works for processors with an out-of-order
backend, for which there is a scheduling model available in LLVM.

The main goal of this tool is not just to predict the performance of the code
when run on the target, but also help with diagnosing potential performance
issues.

Given an assembly code sequence, llvm-mca estimates the IPC (instructions per
cycle), as well as hardware resources pressure. The analysis and reporting style
were mostly inspired by the IACA tool from Intel.

This patch is related to the RFC on llvm-dev visible at this link:
http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html

Differential Revision: https://reviews.llvm.org/D43951


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326998 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 13:05:02 +00:00