7 Commits

Author SHA1 Message Date
Andrea Di Biagio
04b507e104 [llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.

Added extra code comments in class ReadState to better describe each field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334028 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 17:12:02 +00:00
Andrea Di Biagio
8155479799 [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330807 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:38:58 +00:00
Andrea Di Biagio
8ff27dbe39 [llvm-mca] Correctly set the ReadAdvance information for register use operands.
The tool was passing the wrong operand index to method
MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and
not the operand index. This was found when testing X86 code where instructions
had a memory folded operand.

This patch fixes the issue and adds test read-advance-1.s to ensure that
the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328790 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-29 14:26:56 +00:00
Andrea Di Biagio
d7398385c0 [llvm-mca] Minor refactoring. NFCI
Also, removed a couple of unused methods from class Instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328198 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-22 14:14:49 +00:00
Andrea Di Biagio
efac2a8046 [llvm-mca] Simplify (and better standardize) the Instruction interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328190 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-22 11:39:34 +00:00
Andrea Di Biagio
280f00a153 [llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328187 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-22 10:19:20 +00:00
Andrea Di Biagio
29b29cc6a9 [llvm-mca] LLVM Machine Code Analyzer.
llvm-mca is an LLVM based performance analysis tool that can be used to
statically measure the performance of code, and to help triage potential
problems with target scheduling models.

llvm-mca uses information which is already available in LLVM (e.g. scheduling
models) to statically measure the performance of machine code in a specific cpu.
Performance is measured in terms of throughput as well as processor resource
consumption. The tool currently works for processors with an out-of-order
backend, for which there is a scheduling model available in LLVM.

The main goal of this tool is not just to predict the performance of the code
when run on the target, but also help with diagnosing potential performance
issues.

Given an assembly code sequence, llvm-mca estimates the IPC (instructions per
cycle), as well as hardware resources pressure. The analysis and reporting style
were mostly inspired by the IACA tool from Intel.

This patch is related to the RFC on llvm-dev visible at this link:
http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html

Differential Revision: https://reviews.llvm.org/D43951


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326998 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 13:05:02 +00:00