Alex Bradbury d4dc55135e [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr ...

This is a trivial refactoring that I'm committing now as it makes a patch I'm 
about to post for review easier to follow. There is some overlap between 
evaluateConstantImm and addExpr in RISCVAsmParser. This patch allows 
evaluateConstantImm to be reused from addExpr to remove this overlap. The 
benefit will be greater when a future patch adds extra code to allows 
immediates to be evaluated from constant symbols (e.g. `.equ CONST, 0x1234`).

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342641 91177308-0d34-0410-b5e6-96231b3b80d8

2018-09-20 11:40:43 +00:00

..

AsmParser

[RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr

2018-09-20 11:40:43 +00:00

Disassembler

[RISCV] Fix decoding of invalid instruction with C extension enabled.

2018-09-13 18:21:19 +00:00

InstPrinter

[RISCV] Tablegen-driven Instruction Compression.

2018-04-06 21:07:05 +00:00

MCTargetDesc

[Target] Untangle disassemblers

2018-09-10 12:53:46 +00:00

TargetInfo

Fix RISCV build after r318352

2017-11-16 18:39:31 +00:00

CMakeLists.txt

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

LLVMBuild.txt

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCV.h

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCV.td

[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

2018-05-15 01:28:50 +00:00

RISCVAsmPrinter.cpp

Revert "[RISCV] implement li pseudo instruction"

2018-04-18 19:02:31 +00:00

RISCVCallingConv.td

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVExpandPseudoInsts.cpp

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCVFrameLowering.cpp

[RISCV] Fix std::advance slowness

2018-08-24 23:13:59 +00:00

RISCVFrameLowering.h

[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects

2018-03-20 01:39:17 +00:00

RISCVInstrFormats.td

[RISCV] AsmParser support for the li pseudo instruction

2018-06-07 15:35:47 +00:00

RISCVInstrFormatsC.td

[RISCV] MC layer support for the remaining RVC instructions

2017-12-13 09:32:55 +00:00

RISCVInstrInfo.cpp

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVInstrInfo.h

[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

2018-04-26 15:34:27 +00:00

RISCVInstrInfo.td

[RISCV][MC] Improve parsing of jal/j operands

2018-09-20 08:10:35 +00:00

RISCVInstrInfoA.td

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCVInstrInfoC.td

[RISCV] Fix decoding of invalid instruction with C extension enabled.

2018-09-13 18:21:19 +00:00

RISCVInstrInfoD.td

[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}

2018-06-20 14:03:02 +00:00

RISCVInstrInfoF.td

[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode

2018-09-07 18:43:43 +00:00

RISCVInstrInfoM.td

[RISCV] Codegen support for the standard RV32M instruction set extension

2018-01-18 12:36:38 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

RISCVISelLowering.cpp

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCVISelLowering.h

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCVMachineFunctionInfo.h

[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv

2018-04-12 05:34:25 +00:00

RISCVMCInstLower.cpp

[RISCV] Add codegen for RV32F floating point load/store

2018-03-20 13:26:12 +00:00

RISCVMergeBaseOffset.cpp

Test commit.

2018-08-02 05:38:18 +00:00

RISCVRegisterInfo.cpp

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVRegisterInfo.h

[RISCV] Set isReMaterializable on ADDI and LUI instructions

2018-05-17 15:51:37 +00:00

RISCVRegisterInfo.td

[RISCV] Lower the tail pseudoinstruction

2018-05-23 22:44:08 +00:00

RISCVSubtarget.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVSubtarget.h

[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

2018-05-15 01:28:50 +00:00

RISCVTargetMachine.cpp

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

2018-09-19 10:54:22 +00:00

RISCVTargetMachine.h

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVTargetObjectFile.cpp

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00

RISCVTargetObjectFile.h

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00