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2fdd5d3806
Introduce a new RISCVExpandPseudoInsts pass to expand atomic pseudo-instructions after register allocation. This is necessary in order to ensure that register spills aren't introduced between LL and SC, thus breaking the forward progress guarantee for the operation. AArch64 does something similar for CmpXchg (though only at O0), and Mips is moving towards this approach (see D31287). See also [this mailing list post](http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) from James Knight, which summarises the issues with lowering to ll/sc in IR or pre-RA. See the [accompanying RFC thread](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html) for an overview of the lowering strategy. Differential Revision: https://reviews.llvm.org/D47882 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342534 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.4 KiB
C++
46 lines
1.4 KiB
C++
//===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// RISC-V back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
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#define LLVM_LIB_TARGET_RISCV_RISCV_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class RISCVTargetMachine;
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class AsmPrinter;
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class FunctionPass;
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class MCInst;
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class MCOperand;
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class MachineInstr;
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class MachineOperand;
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class PassRegistry;
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void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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const AsmPrinter &AP);
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bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp, const AsmPrinter &AP);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
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FunctionPass *createRISCVMergeBaseOffsetOptPass();
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void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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FunctionPass *createRISCVExpandPseudoPass();
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void initializeRISCVExpandPseudoPass(PassRegistry &);
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}
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#endif
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