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837d4755cd
Summary: We generate s_xor to lower add of i1s in general cases, and s_not to lower add with a one-bit imm of -1 (true). Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D52518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343030 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
694 B
LLVM
22 lines
694 B
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}add_var_var_i1:
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; GCN: s_xor_b64
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define amdgpu_kernel void @add_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
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%a = load volatile i1, i1 addrspace(1)* %in0
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%b = load volatile i1, i1 addrspace(1)* %in1
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%add = add i1 %a, %b
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store i1 %add, i1 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_var_imm_i1:
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; GCN: s_not_b64
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define amdgpu_kernel void @add_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
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%a = load volatile i1, i1 addrspace(1)* %in
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%add = add i1 %a, 1
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store i1 %add, i1 addrspace(1)* %out
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ret void
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}
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