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d566da724a
Mark the FREM SelectionDAG node as Expand, which is necessary in order to support the frem IR instruction on RISC-V. This is expanded into a library call. Adds the corresponding test. Previously, this would have triggered an assertion at instruction selection time. Differential Revision: https://reviews.llvm.org/D54159 Patch by Luís Marques. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346958 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
522 B
LLVM
17 lines
522 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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define float @frem_f32(float %a, float %b) nounwind {
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; RV32IF-LABEL: frem_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: call fmodf
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; RV32IF-NEXT: lw ra, 12(sp)
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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%1 = frem float %a, %b
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ret float %1
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}
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