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78e3c70281
Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335786 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
3.3 KiB
C++
105 lines
3.3 KiB
C++
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about RISCV target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "RISCVTargetObjectFile.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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}
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static std::string computeDataLayout(const Triple &TT) {
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if (TT.isArch64Bit()) {
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return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
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} else {
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assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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return "e-m:e-p:32:32-i64:64-n32-S128";
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}
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM),
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getEffectiveCodeModel(CM), OL),
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TLOF(make_unique<RISCVELFTargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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namespace {
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class RISCVPassConfig : public TargetPassConfig {
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public:
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RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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RISCVTargetMachine &getRISCVTargetMachine() const {
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return getTM<RISCVTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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}
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TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new RISCVPassConfig(*this, PM);
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}
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void RISCVPassConfig::addIRPasses() {
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addPass(createAtomicExpandPass());
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TargetPassConfig::addIRPasses();
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}
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bool RISCVPassConfig::addInstSelector() {
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addPass(createRISCVISelDag(getRISCVTargetMachine()));
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return false;
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}
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void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
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void RISCVPassConfig::addPreRegAlloc() {
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addPass(createRISCVMergeBaseOffsetOptPass());
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}
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