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a6a5be21df
This reverts commit r311038. Several buildbots are breaking, and at least one appears to be due to the forwarding of physical regs enabled by this change. Reverting while I investigate further. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311062 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.8 KiB
LLVM
57 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
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; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=OPTNONE %s
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; There are no stack objects, but still a private memory access. The
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; private access regiters need to be correctly initialized anyway, and
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; shifted down to the end of the used registers.
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; GCN-LABEL: {{^}}store_to_undef:
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; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
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; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
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; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
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; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
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; -O0 should assume spilling, so the input scratch resource descriptor
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; -should be used directly without any copies.
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; OPTNONE-NOT: s_mov_b32
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; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}}
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define amdgpu_kernel void @store_to_undef() #0 {
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store volatile i32 0, i32* undef
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ret void
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}
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; GCN-LABEL: {{^}}store_to_inttoptr:
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; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
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; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
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; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
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; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
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define amdgpu_kernel void @store_to_inttoptr() #0 {
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store volatile i32 0, i32* inttoptr (i32 124 to i32*)
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ret void
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}
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; GCN-LABEL: {{^}}load_from_undef:
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; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
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; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
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; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
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; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
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define amdgpu_kernel void @load_from_undef() #0 {
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%ld = load volatile i32, i32* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_from_inttoptr:
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; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
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; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
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; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
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; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
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define amdgpu_kernel void @load_from_inttoptr() #0 {
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%ld = load volatile i32, i32* inttoptr (i32 124 to i32*)
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ret void
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}
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attributes #0 = { nounwind }
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