llvm/MC at 043998b329efeb8efdd2aed58a2e6ee38f6b3fdc - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-02-08 03:26:34 +00:00

History

Oliver Stannard 132e2d3b5c [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB

This adds 2-operand assembly aliases for these instructions:
  add r0, r1    =>   add r0, r0, r1
  sub r0, r1    =>   sub r0, r0, r1

Previously this syntax was only accepted for Thumb2 targets, where the
wide versions of the instructions were used.

This patch allows the 2-operand syntax to be used for Thumb1 targets,
and selects the narrow encoding when it is used for Thumb2 targets.

Differential revision: https://reviews.llvm.org/D37377



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312321 91177308-0d34-0410-b5e6-96231b3b80d8

2017-09-01 10:47:25 +00:00

AArch64

[AArch64] v8.3-a complex number support

2017-08-31 09:27:04 +00:00

AMDGPU

AMDGPU: Correct operand types for v_mad_mix*

2017-08-30 22:18:40 +00:00

ARM

[ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB

2017-09-01 10:47:25 +00:00

AsmParser

[AsmParser] Recommit: Hash is not a comment on some targets