Krzysztof Parzyszek 422399f9c7 Add test/CodeGen/MIR/Hexagon/lit.local.cfg ... Require that Hexagon is a registered target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270887 91177308-0d34-0410-b5e6-96231b3b80d8		2016-05-26 18:35:45 +00:00
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AArch64	[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()	2016-03-31 20:53:47 +00:00
AMDGPU	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
ARM	ARM: fix handling of SUB immediates in peephole opt.	2016-05-02 18:30:08 +00:00
Generic	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00
Hexagon	Add test/CodeGen/MIR/Hexagon/lit.local.cfg	2016-05-26 18:35:45 +00:00
Mips	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
NVPTX	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
PowerPC	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
X86	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00