Jakob Stoklund Olesen 4662a9f270 Allow coalescing with reserved physregs in certain cases: ... When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128845 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-04 21:00:03 +00:00
..
Alpha	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
ARM	Do some peephole optimizations to remove pointless VMOVs from Neon to integer	2011-04-02 02:40:43 +00:00
Blackfin	Don't completely eliminate identity copies that also modify super register liveness.	2011-03-31 17:55:25 +00:00
CBackend
CellSPU	Roll r127459 back in:	2011-03-11 21:52:04 +00:00
CPP
Generic	Make this test x86 specific because the ARM backend can't handle it.	2011-02-28 12:30:47 +00:00
MBlaze	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
Mips	Add code for analyzing FP branches. Clean up branch Analysis functions.	2011-04-01 17:39:08 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC	Disable the PowerPC/Atomics-64 test.	2011-04-04 17:57:26 +00:00
PTX	ptx: support setp's 4-operand format	2011-04-02 08:51:39 +00:00
SPARC	Fix Mips, Sparc, and XCore tests that were dependent on register allocation.	2011-03-31 18:42:43 +00:00
SystemZ	Fix SystemZ tests	2011-03-31 23:02:12 +00:00
Thumb	Fix Thumb and Thumb2 tests to be register allocator independent.	2011-03-31 23:31:50 +00:00
Thumb2	Fix Thumb and Thumb2 tests to be register allocator independent.	2011-03-31 23:31:50 +00:00
X86	Allow coalescing with reserved physregs in certain cases:	2011-04-04 21:00:03 +00:00
XCore	Fix Mips, Sparc, and XCore tests that were dependent on register allocation.	2011-03-31 18:42:43 +00:00