Hao Liu 1a080cef90 [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-07 10:50:43 +00:00
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AArch64	[AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.	2014-01-07 10:50:43 +00:00
ARM	ARM IAS: improve .eabi_attribute handling	2014-01-07 02:28:42 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	Remove a failing test to get the buildbots back to green.	2014-01-06 00:43:09 +00:00
Hexagon
Inputs
Mips	[Mips] Does not take in account 'use-soft-float' attribute's value when	2013-12-25 17:00:27 +00:00
MSP430
NVPTX
PowerPC	Implement initial-exec TLS for PPC32.	2013-12-20 18:08:54 +00:00
R600	R600: Allow ftrunc	2013-12-20 05:11:55 +00:00
SPARC	[SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.	2014-01-04 07:17:21 +00:00
SystemZ	[SystemZ] Use interlocked-access 1 instructions for CodeGen	2013-12-24 15:18:04 +00:00
Thumb	Correctly handle the degenerated triple "thumb".	2013-12-18 21:29:44 +00:00
Thumb2
X86	Fix for PR18396: Assertion: MO->isDead "Cannot fold physreg def".	2014-01-07 07:31:10 +00:00
XCore	XCore Target: correct callee save register spilling when callsUnwindInit is true.	2014-01-06 14:21:12 +00:00