Alex Bradbury 2bd791038b [TableGen] Give the option of tolerating duplicate register names ...

A number of architectures re-use the same register names (e.g. for both 32-bit 
FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated 
MatchRegisterName and MatchRegisterAltName, as tablegen (when built with 
asserts enabled) will fail.

When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register 
names will be tolerated. A backend can then coerce registers to the desired 
register class by (for instance) implementing validateTargetOperandClass.

At least the in-tree Sparc backend could benefit from this, as does RISC-V 
(single and double precision floating point registers).

Differential Revision: https://reviews.llvm.org/D39845


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320018 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-07 09:51:55 +00:00

..

CMakeLists.txt

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Error.cpp

[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.

2017-11-01 22:13:05 +00:00

LLVMBuild.txt

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Main.cpp

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Record.cpp

Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.

2017-10-15 14:32:27 +00:00

SetTheory.cpp

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StringMatcher.cpp

[TableGen] Give the option of tolerating duplicate register names

2017-12-07 09:51:55 +00:00

TableGenBackend.cpp

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TGLexer.cpp

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TGLexer.h

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TGParser.cpp

Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.

2017-10-15 14:32:27 +00:00

TGParser.h

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