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2b4ea795a2
llvm/lib/Target/Alpha
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Evan Cheng 2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-26 09:11:45 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
Alpha.h ret 0; works, not much else 2005-10-20 00:28:31 +00:00
Alpha.td Add attribute name and type to SubtargetFeatures. 2005-10-26 17:28:23 +00:00
AlphaAsmPrinter.cpp add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 2005-12-25 17:36:48 +00:00
AlphaCodeEmitter.cpp massive DAGISel patch. lots and lots more stuff compiles now 2005-11-22 04:20:06 +00:00
AlphaInstrFormats.td add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 2005-12-25 17:36:48 +00:00
AlphaInstrInfo.cpp whatever. Intermediate patch to see what breaks. Seems ok. 2005-11-09 19:17:08 +00:00
AlphaInstrInfo.h Remove trailing whitespace 2005-04-21 23:13:11 +00:00
AlphaInstrInfo.td Added field noResults to Instruction. 2005-12-26 09:11:45 +00:00
AlphaISelDAGToDAG.cpp add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 2005-12-25 17:36:48 +00:00
AlphaISelLowering.cpp All that just to lower div and rem 2005-12-25 01:34:27 +00:00
AlphaISelLowering.h All that just to lower div and rem 2005-12-25 01:34:27 +00:00
AlphaISelPattern.cpp add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 2005-12-25 17:36:48 +00:00
AlphaJITInfo.cpp No, IDEFs shouldn't be JITed 2005-08-04 15:32:36 +00:00
AlphaJITInfo.h Alpha JIT (beta) 2005-07-22 20:52:16 +00:00
AlphaRegisterInfo.cpp whatever. Intermediate patch to see what breaks. Seems ok. 2005-11-09 19:17:08 +00:00
AlphaRegisterInfo.h whatever. Intermediate patch to see what breaks. Seems ok. 2005-11-09 19:17:08 +00:00
AlphaRegisterInfo.td Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
AlphaRelocations.h support bsr, and more .td simplification 2005-07-28 18:14:47 +00:00
AlphaSubtarget.cpp Give full control of subtarget features over to table generated code. 2005-10-26 17:30:34 +00:00
AlphaSubtarget.h Typo made worse x 2 - take 2. 2005-10-26 18:07:50 +00:00
AlphaTargetMachine.cpp prevent latent switch creation 2005-11-18 13:57:03 +00:00
AlphaTargetMachine.h Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build. 2005-11-08 02:11:51 +00:00
Makefile Autogen subtarget information from .td files. 2005-10-23 22:15:34 +00:00