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defd4bc77b
profitability check due to some other checks in the addressing mode matcher. I.e., test case for commit r201121. <rdar://problem/16020230> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201132 91177308-0d34-0410-b5e6-96231b3b80d8
304 lines
12 KiB
LLVM
304 lines
12 KiB
LLVM
; RUN: opt -S -codegenprepare %s -o - | FileCheck %s
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; This file tests the different cases what are involved when codegen prepare
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; tries to get sign extension out of the way of addressing mode.
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; This tests require an actual target as addressing mode decisions depends
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; on the target.
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target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx"
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; Check that we correctly promote both operands of the promotable add.
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; CHECK-LABEL: @twoArgsPromotion
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
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; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], [[ARG2SEXT]]
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; CHECK: inttoptr i64 [[PROMOTED]] to i8*
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; CHECK: ret
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define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) {
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%add = add nsw i32 %arg1, %arg2
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%sextadd = sext i32 %add to i64
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%base = inttoptr i64 %sextadd to i8*
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%res = load i8* %base
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ret i8 %res
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}
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; Check that we do not promote both operands of the promotable add when
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; the instruction will not be folded into the addressing mode.
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; Otherwise, we will increase the number of instruction executed.
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; (This is a heuristic of course, because the new sext could have been
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; merged with something else.)
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; CHECK-LABEL: @twoArgsNoPromotion
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; CHECK: add nsw i32 %arg1, %arg2
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; CHECK: ret
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define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, i8* %base) {
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%add = add nsw i32 %arg1, %arg2
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%sextadd = sext i32 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Check that we do not promote when the related instruction does not have
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; the nsw flag.
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; CHECK-LABEL: @noPromotion
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; CHECK-NOT: add i64
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; CHECK: ret
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define i8 @noPromotion(i32 %arg1, i32 %arg2, i8* %base) {
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%add = add i32 %arg1, %arg2
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%sextadd = sext i32 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Check that we correctly promote constant arguments.
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; CHECK-LABEL: @oneArgPromotion
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: ret
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define i8 @oneArgPromotion(i32 %arg1, i8* %base) {
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%add = add nsw i32 %arg1, 1
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%sextadd = sext i32 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Check that we do not promote truncate when we cannot determine the
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; bits that are dropped.
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; CHECK-LABEL: @oneArgPromotionBlockTrunc1
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; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: ret
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define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, i8* %base) {
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%trunc = trunc i32 %arg1 to i8
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%add = add nsw i8 %trunc, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Check that we do not promote truncate when we cannot determine all the
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; bits that are dropped.
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; CHECK-LABEL: @oneArgPromotionBlockTrunc2
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i16 %arg1 to i32
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; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8
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; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
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; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: ret
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define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, i8* %base) {
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%sextarg1 = sext i16 %arg1 to i32
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%trunc = trunc i32 %sextarg1 to i8
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%add = add nsw i8 %trunc, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Check that we are able to promote truncate when we know all the bits
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; that are dropped.
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; CHECK-LABEL: @oneArgPromotionPassTruncKeepSExt
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: ret
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define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, i8* %base) {
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%sextarg1 = sext i1 %arg1 to i32
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%trunc = trunc i32 %sextarg1 to i8
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%add = add nsw i8 %trunc, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; On X86 truncate are free. Check that we are able to promote the add
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; to be used as addressing mode and that we insert a truncate for the other
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; use.
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; CHECK-LABEL: @oneArgPromotionTruncInsert
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
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; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
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; CHECK: add i8 [[LOAD]], [[TRUNC]]
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; CHECK: ret
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define i8 @oneArgPromotionTruncInsert(i8 %arg1, i8* %base) {
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%add = add nsw i8 %arg1, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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%finalres = add i8 %res, %add
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ret i8 %finalres
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}
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; Cannot sext from a larger type than the promoted type.
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; CHECK-LABEL: @oneArgPromotionLargerType
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; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i128 %arg1 to i8
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; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
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; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: ret
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define i8 @oneArgPromotionLargerType(i128 %arg1, i8* %base) {
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%trunc = trunc i128 %arg1 to i8
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%add = add nsw i8 %trunc, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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%finalres = add i8 %res, %add
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ret i8 %finalres
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}
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; Use same inserted trunc
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; On X86 truncate are free. Check that we are able to promote the add
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; to be used as addressing mode and that we insert a truncate for
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; *all* the other uses.
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; CHECK-LABEL: @oneArgPromotionTruncInsertSeveralUse
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
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; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
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; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = add i8 [[LOAD]], [[TRUNC]]
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; CHECK: add i8 [[ADDRES]], [[TRUNC]]
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; CHECK: ret
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define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, i8* %base) {
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%add = add nsw i8 %arg1, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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%almostfinalres = add i8 %res, %add
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%finalres = add i8 %almostfinalres, %add
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ret i8 %finalres
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}
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; Check that the promoted instruction is used for all uses of the original
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; sign extension.
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; CHECK-LABEL: @oneArgPromotionSExtSeveralUse
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; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
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; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
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; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
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; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
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; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = zext i8 [[LOAD]] to i64
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; CHECK: add i64 [[ADDRES]], [[PROMOTED]]
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; CHECK: ret
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define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, i8* %base) {
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%add = add nsw i8 %arg1, 1
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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%almostfinalres = zext i8 %res to i64
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%finalres = add i64 %almostfinalres, %sextadd
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ret i64 %finalres
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}
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; Check all types of rollback mechanism.
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; For this test, the sign extension stays in place.
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; However, the matching process goes until promoting both the operands
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; of the first promotable add implies.
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; At this point the rollback mechanism kicks in and restores the states
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; until the addressing mode matcher is able to match something: in that
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; case promote nothing.
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; Along the way, the promotion mechanism involves:
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; - Mutating the type of %promotableadd1 and %promotableadd2.
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; - Creating a sext for %arg1 and %arg2.
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; - Creating a trunc for a use of %promotableadd1.
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; - Replacing a bunch of uses.
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; - Setting the operands of the promoted instruction with the promoted values.
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; - Moving instruction around (mainly sext when promoting instruction).
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; Each type of those promotions has to be undo at least once during this
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; specific test.
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; CHECK-LABEL: @twoArgsPromotionNest
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; CHECK: [[ORIG:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2
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; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ORIG]], [[ORIG]]
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; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
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; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
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; CHECK: ret
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define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, i8* %base) {
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%promotableadd1 = add nsw i32 %arg1, %arg2
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%promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1
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%sextadd = sext i32 %promotableadd2 to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Test the InstructionRemover undo, which was the only one not
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; kicked in the previous test.
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; The matcher first promotes the add, removes the trunc and promotes
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; the sext of arg1.
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; Then, the matcher cannot use an addressing mode r + r + r, thus it
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; rolls back.
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; CHECK-LABEL: @twoArgsNoPromotionRemove
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; CHECK: [[SEXTARG1:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32
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; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[SEXTARG1]] to i8
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; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[TRUNC]], %arg2
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; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64
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; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
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; CHECK: ret
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define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
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%sextarg1 = sext i1 %arg1 to i32
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%trunc = trunc i32 %sextarg1 to i8
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%add = add nsw i8 %trunc, %arg2
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%sextadd = sext i8 %add to i64
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%arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Ensure that when the profitability checks kicks in, the IR is not modified
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; will IgnoreProfitability is on.
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; The profitabily check happens when a candidate instruction has several uses.
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; The matcher will create a new matcher for each use and check if the
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; instruction is in the list of the matched instructions of this new matcher.
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; All changes made by the new matchers must be dropped before pursuing
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; otherwise the state of the original matcher will be wrong.
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;
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; Without the profitability check, when checking for the second use of
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; arrayidx, the matcher promotes everything all the way to %arg1, %arg2.
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; Check that we did not promote anything in the final matching.
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;
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; <rdar://problem/16020230>
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; CHECK-LABEL: @checkProfitability
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; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64
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; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64
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; CHECK: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1
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; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2
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; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
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; BB then
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; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
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; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32*
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; CHECK: load i32* [[ADDR1]]
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; BB else
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; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
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; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE2]] to i32*
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; CHECK: load i32* [[ADDR2]]
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; CHECK: ret
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define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) {
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%shl = shl nsw i32 %arg1, 1
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%add1 = add nsw i32 %shl, %arg2
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%sextidx1 = sext i32 %add1 to i64
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%tmpptr = inttoptr i64 %sextidx1 to i32*
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%arrayidx1 = getelementptr i32* %tmpptr, i64 12
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br i1 %test, label %then, label %else
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then:
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%res1 = load i32* %arrayidx1
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br label %end
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else:
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%res2 = load i32* %arrayidx1
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br label %end
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end:
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%tmp = phi i32 [%res1, %then], [%res2, %else]
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%res = add i32 %tmp, %add1
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%addr = inttoptr i32 %res to i32*
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%final = load i32* %addr
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ret i32 %final
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}
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