Craig Topper 3ed535e977 [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
These instructions only read 64-bits of memory so we shouldn't
allow a full vector width load to be pattern matched in case it
is marked volatile.

Instead allow vzload or scalar_to_vector+load.

Also add a DAG combine to turn full vector loads into vzload when
used by one of these instructions if the load isn't volatile.

This fixes another case for PR42079

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364838 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-01 19:01:37 +00:00
2014-03-02 13:08:46 +00:00
2016-01-26 21:29:08 +00:00
2019-02-19 20:38:51 +00:00

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