Matt Arsenault ac9b3ef76a AMDGPU: Add Vega12 and Vega20 ... Changes by Matt Arsenault Konstantin Zhuravlyov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331215 91177308-0d34-0410-b5e6-96231b3b80d8		2018-04-30 19:08:16 +00:00
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AArch64	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AMDGPU	AMDGPU: Add Vega12 and Vega20	2018-04-30 19:08:16 +00:00
ARC	[ARC] Add LImm support for J/JL	2018-04-13 15:10:34 +00:00
ARM	[ARM]Decoding MSR with unpredictable destination register causes an assert	2018-03-06 15:21:19 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai
Mips	[mips] Add support for Virtualization ASE	2018-04-27 09:12:08 +00:00
PowerPC	[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.	2018-02-23 15:55:16 +00:00
Sparc
SystemZ
X86	[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.	2018-04-29 06:24:09 +00:00
XCore