Simi Pallipurath 0cf7d296a2 [ARM]Decoding MSR with unpredictable destination register causes an assert ... This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8		2018-03-06 15:21:19 +00:00
..
addrmode2-reencoding.txt
arm-LDREXD-reencoding.txt
arm-STREXD-reencoding.txt
arm-tests.txt
arm-thumb-trustzone.txt
arm-trustzone.txt
arm-vmrs_vmsr.txt	[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode	2017-10-18 14:47:37 +00:00
armv8.1a.txt
armv8.2a-dotprod-a32.s	[ARM] Assembler support for the ARMv8.2a dot product instructions	2017-08-11 09:52:30 +00:00
armv8.2a-dotprod-t32.s	[ARM] Assembler support for the ARMv8.2a dot product instructions	2017-08-11 09:52:30 +00:00
armv8.3a-js-arm.txt	[ARM][AArch64] v8.3-A Javascript Conversion	2017-08-22 11:08:21 +00:00
armv8.3a-js-thumb.txt	[ARM][AArch64] v8.3-A Javascript Conversion	2017-08-22 11:08:21 +00:00
basic-arm-instructions-v8.txt
basic-arm-instructions.txt
crc32-thumb.txt
crc32.txt
csdb-arm.txt	[ARM][AArch64] Add CSDB speculation barrier instruction	2018-02-06 09:24:47 +00:00
csdb-thumb.txt	[ARM][AArch64] Add CSDB speculation barrier instruction	2018-02-06 09:24:47 +00:00
d16.txt
dfb-arm.txt	[ARM] Armv8-R DFB instruction	2017-12-21 11:17:49 +00:00
dfb-thumb.txt	[ARM] Armv8-R DFB instruction	2017-12-21 11:17:49 +00:00
fp-armv8.txt
fp-encoding.txt
fullfp16-arm-neg.txt
fullfp16-arm.txt
fullfp16-neon-arm-neg.txt
fullfp16-neon-arm.txt
fullfp16-neon-thumb-neg.txt
fullfp16-neon-thumb.txt
fullfp16-thumb-neg.txt
fullfp16-thumb.txt
hex-immediates.txt
invalid-armv7.txt	[ARM] Re-commit r324600 with fixed LLVMBuild.txt	2018-02-08 14:31:22 +00:00
invalid-armv8.1a.txt
invalid-armv8.txt
invalid-because-armv7.txt
invalid-FSTMX-arm.txt
invalid-IT-CC15.txt
invalid-thumb-MSR-MClass.txt	[ARM]Decoding MSR with unpredictable destination register causes an assert	2018-03-06 15:21:19 +00:00
invalid-thumbv7-xfail.txt
invalid-thumbv7.txt	[ARM] Re-commit r324600 with fixed LLVMBuild.txt	2018-02-08 14:31:22 +00:00
invalid-thumbv8.1a.txt
invalid-thumbv8.txt
invalid-virtexts.arm.txt
ldrd-armv4.txt
lit.local.cfg
load-store-acquire-release-v8-thumb.txt
load-store-acquire-release-v8.txt
marked-up-thumb.txt
memory-arm-instructions.txt
move-banked-regs-arm.txt
move-banked-regs-thumb.txt
neon-complex-arm.txt	[ARM] v8.3-a complex number support	2017-09-29 13:11:33 +00:00
neon-complex-thumb.txt	[ARM] v8.3-a complex number support	2017-09-29 13:11:33 +00:00
neon-crypto.txt
neon-tests.txt
neon-v8.txt
neon.txt
neont2.txt
neont-VLD-reencoding.txt
neont-VST-reencoding.txt
ras-extension-arm.txt
ras-extension-thumb.txt
thumb1.txt
thumb2-preloads.txt
thumb2-v8.txt
thumb2-v8m.txt
thumb2.txt
thumb-fp-armv8.txt
thumb-MSR-MClass.txt
thumb-neon-crypto.txt
thumb-neon-v8.txt
thumb-printf.txt
thumb-tests.txt
thumb-v8.1a.txt
thumb-v8.txt
thumb-vmrs_vmsr.txt	[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode	2017-10-18 14:47:37 +00:00
unpredictable-ADC-arm.txt
unpredictable-ADDREXT3-arm.txt
unpredictable-AExtI-arm.txt
unpredictable-AI1cmp-arm.txt
unpredictable-BFI.txt
unpredictable-LDR-arm.txt
unpredictable-LDRD-arm.txt
unpredictable-LSL-regform.txt
unpredictable-MRRC2-arm.txt
unpredictable-MRS-arm.txt
unpredictable-MUL-arm.txt
unpredictable-MVN-arm.txt	[ARM] Add support for unpredictable MVN instructions.	2018-02-01 12:06:57 +00:00
unpredictable-RSC-arm.txt
unpredictable-SEL-arm.txt
unpredictable-SHADD16-arm.txt
unpredictable-SSAT-arm.txt
unpredictable-STRBrs-arm.txt
unpredictable-swp-arm.txt
unpredictable-UQADD8-arm.txt
unpredictables-thumb.txt
vfp4.txt
virtexts-arm.txt
virtexts-thumb.txt