llvm/lib/CodeGen
2009-07-20 19:47:55 +00:00
..
AsmPrinter implement a new magic global "llvm.compiler.used" which is like llvm.used, but 2009-07-20 06:14:25 +00:00
SelectionDAG Fix some minor MSVC compiler warnings. 2009-07-19 01:38:38 +00:00
BranchFolding.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
CMakeLists.txt Fix the cmake build - patch by Xerxes Rånby. 2009-07-06 14:28:32 +00:00
CodePlacementOpt.cpp
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp Revert yesterday's change by removing the LLVMContext parameter to AllocaInst and MallocInst. 2009-07-15 23:53:25 +00:00
ELF.h Add support to properly reference private symbols on relocation entries. 2009-07-18 19:30:09 +00:00
ELFCodeEmitter.cpp Use R_X86_64_32S to handle Jump Table Index relocation entries. Hide TAI usage inside getSection* functions 2009-07-18 23:24:01 +00:00
ELFCodeEmitter.h Changed ELFCodeEmitter to inherit from ObjectCodeEmitter 2009-07-06 09:26:48 +00:00
ELFWriter.cpp For PC relative relocations where symbols are defined in the same section they 2009-07-20 08:52:02 +00:00
ELFWriter.h For PC relative relocations where symbols are defined in the same section they 2009-07-20 08:52:02 +00:00
GCMetadata.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
IfConversion.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
IntrinsicLowering.cpp Move EVER MORE stuff over to LLVMContext. 2009-07-14 23:09:55 +00:00
LatencyPriorityQueue.cpp
LazyLiveness.cpp
LiveInterval.cpp Improved tracking of value number kills. VN kills are now represented 2009-07-09 03:57:02 +00:00
LiveIntervalAnalysis.cpp Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. 2009-07-17 19:43:40 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Avoid adding a duplicate def. This fixes PR4478. 2009-07-06 21:34:05 +00:00
LLVMTargetMachine.cpp We don't need to use llvm_report_error, this interface can deal with errors 2009-07-15 23:54:01 +00:00
LowerSubregs.cpp Let RegisterInfo decide whether it can emit cross-class copy or not 2009-07-16 13:55:26 +00:00
MachineBasicBlock.cpp
MachineDominators.cpp
MachineFunction.cpp Add an "alignment" field to the MachineFunction object. It makes more sense to 2009-06-30 22:38:32 +00:00
MachineInstr.cpp Fix http://llvm.org/bugs/show_bug.cgi?id=4583 2009-07-19 19:09:59 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp Make Loop and MachineLoop be subclasses of LoopBase, rather than typedefs, 2009-07-13 21:51:15 +00:00
MachineModuleInfo.cpp implement a new magic global "llvm.compiler.used" which is like llvm.used, but 2009-07-20 06:14:25 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
MachineVerifier.cpp Verify that there is no kill flag on tied operands on two-address instructions. 2009-07-15 23:37:26 +00:00
MachO.h Cleanup MachO writer and code emitter. Fix 80 cols problems, remove extra spaces, shrink down includes and move some methods out-of-line 2009-07-06 06:40:51 +00:00
MachOCodeEmitter.cpp Reapply my previous asmprinter changes now with more testing and two 2009-07-14 18:17:16 +00:00
MachOCodeEmitter.h Cleanup MachO writer and code emitter. Fix 80 cols problems, remove extra spaces, shrink down includes and move some methods out-of-line 2009-07-06 06:40:51 +00:00
MachOWriter.cpp Add plumbing for the `linker_private' linkage type. This type is meant for 2009-07-20 01:03:30 +00:00
MachOWriter.h Match declaration to definition (missed a few). 2009-07-13 06:04:06 +00:00
Makefile
ObjectCodeEmitter.cpp Just forgot to include the two new files 2009-07-06 05:16:40 +00:00
OcamlGC.cpp
Passes.cpp
PBQP.cpp
PBQP.h
PHIElimination.cpp Revert 74898. It broke several tests. 2009-07-07 17:50:43 +00:00
PostRASchedulerList.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
PreAllocSplitting.cpp Let callers decide the sub-register index on the def operand of rematerialized instructions. 2009-07-16 09:20:10 +00:00
PrologEpilogInserter.cpp Add support for naked functions 2009-07-17 18:07:26 +00:00
PrologEpilogInserter.h Scan for presence of calls and determine max callframe size early. To allow ProcessFunctionBeforeCalleeSaveScan() use this information 2009-07-16 13:50:40 +00:00
PseudoSourceValue.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
README.txt
RegAllocBigBlock.cpp
RegAllocLinearScan.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
RegAllocLocal.cpp Convert more assert(0)+abort() -> LLVM_UNREACHABLE, 2009-07-11 13:10:19 +00:00
RegAllocPBQP.cpp VNInfo cleanup. 2009-06-17 21:01:20 +00:00
RegAllocSimple.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp Fix bug in RegScavenger::scavengeRegister(). 2009-07-15 22:32:11 +00:00
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Eliminate yet another copy of getOpcode. 2009-07-17 20:58:59 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp Get rid of the global CFGOnly flag by threading a ShortNames parameters through the GraphViz rendering code. 2009-06-24 17:37:09 +00:00
ShadowStackGC.cpp Move EVER MORE stuff over to LLVMContext. 2009-07-14 23:09:55 +00:00
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 2009-07-20 19:47:55 +00:00
SimpleRegisterCoalescing.h Simplify some more. 2009-07-17 21:06:58 +00:00
Spiller.cpp Improved tracking of value number kills. VN kills are now represented 2009-07-09 03:57:02 +00:00
Spiller.h Fix some minor MSVC compiler warnings. 2009-07-19 01:38:38 +00:00
StackProtector.cpp Revert yesterday's change by removing the LLVMContext parameter to AllocaInst and MallocInst. 2009-07-15 23:53:25 +00:00
StackSlotColoring.cpp Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 2009-07-17 22:42:51 +00:00
StrongPHIElimination.cpp Improved tracking of value number kills. VN kills are now represented 2009-07-09 03:57:02 +00:00
TargetInstrInfoImpl.cpp Let callers decide the sub-register index on the def operand of rematerialized instructions. 2009-07-16 09:20:10 +00:00
TwoAddressInstructionPass.cpp Let callers decide the sub-register index on the def operand of rematerialized instructions. 2009-07-16 09:20:10 +00:00
UnreachableBlockElim.cpp Begin the painful process of tearing apart the rat'ss nest that is Constants.cpp and ConstantFold.cpp. 2009-07-13 04:09:18 +00:00
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Enable cross register class coalescing. 2009-07-18 02:10:10 +00:00
VirtRegRewriter.h Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), removed old TODO comments. 2009-06-24 02:17:32 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4