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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
5.1 KiB
TableGen
122 lines
5.1 KiB
TableGen
//===-- HexagoSelectCCInfo.td - Selectcc mappings ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// selectcc mappings.
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//
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETEQ)),
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(i32 (MUX_rr (i1 (CMPEQrr IntRegs:$lhs, IntRegs:$rhs)),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETNE)),
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(i32 (MUX_rr (i1 (NOT_p (CMPEQrr IntRegs:$lhs, IntRegs:$rhs))),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETGT)),
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(i32 (MUX_rr (i1 (CMPGTrr IntRegs:$lhs, IntRegs:$rhs)),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETUGT)),
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(i32 (MUX_rr (i1 (CMPGTUrr IntRegs:$lhs, IntRegs:$rhs)),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETULT)),
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(i32 (MUX_rr (i1 (NOT_p (CMPGTUrr IntRegs:$lhs,
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(ADD_ri IntRegs:$rhs, -1)))),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETLT)),
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(i32 (MUX_rr (i1 (NOT_p (CMPGTrr IntRegs:$lhs,
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(ADD_ri IntRegs:$rhs, -1)))),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETLE)),
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(i32 (MUX_rr (i1 (NOT_p (CMPGTrr IntRegs:$lhs, IntRegs:$rhs))),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETULE)),
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(i32 (MUX_rr (i1 (NOT_p (CMPGTUrr IntRegs:$lhs, IntRegs:$rhs))),
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IntRegs:$tval, IntRegs:$fval))>;
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//
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// selectcc mappings for greater-equal-to Rs => greater-than Rs-1.
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//
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETGE)),
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(i32 (MUX_rr (i1 (CMPGTrr IntRegs:$lhs, (ADD_ri IntRegs:$rhs, -1))),
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IntRegs:$tval, IntRegs:$fval))>;
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def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETUGE)),
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(i32 (MUX_rr (i1 (CMPGTUrr IntRegs:$lhs, (ADD_ri IntRegs:$rhs, -1))),
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IntRegs:$tval, IntRegs:$fval))>;
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//
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// selectcc mappings for predicate comparisons.
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//
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// Convert Rd = selectcc(p0, p1, true_val, false_val, SETEQ) into:
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// pt = not(p1 xor p2)
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// Rd = mux(pt, true_val, false_val)
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// and similarly for SETNE
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//
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def : Pat <(i32 (selectcc PredRegs:$lhs, PredRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETNE)),
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(i32 (MUX_rr (i1 (XOR_pp PredRegs:$lhs, PredRegs:$rhs)), IntRegs:$tval,
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IntRegs:$fval))>;
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def : Pat <(i32 (selectcc PredRegs:$lhs, PredRegs:$rhs, IntRegs:$tval,
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IntRegs:$fval, SETEQ)),
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(i32 (MUX_rr (i1 (NOT_p (XOR_pp PredRegs:$lhs, PredRegs:$rhs))),
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IntRegs:$tval, IntRegs:$fval))>;
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//
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// selectcc mappings for 64-bit operands are messy. Hexagon does not have a
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// MUX64 o, use this:
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// selectcc(Rss, Rdd, tval, fval, cond) ->
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// combine(mux(cmp_cond(Rss, Rdd), tval.hi, fval.hi),
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// mux(cmp_cond(Rss, Rdd), tval.lo, fval.lo))
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// setgt-64.
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def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
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DoubleRegs:$fval, SETGT)),
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(COMBINE_rr (MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
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(EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
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(EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
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(MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
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(EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
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(EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
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// setlt-64 -> setgt-64.
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def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
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DoubleRegs:$fval, SETLT)),
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(COMBINE_rr (MUX_rr (CMPGT64rr DoubleRegs:$lhs,
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(ADD64_rr DoubleRegs:$rhs, (TFRI64 -1))),
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(EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
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(EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
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(MUX_rr (CMPGT64rr DoubleRegs:$lhs,
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(ADD64_rr DoubleRegs:$rhs, (TFRI64 -1))),
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(EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
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(EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
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