llvm/lib/Target/CellSPU
Bill Wendling 587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
..
AsmPrinter Rename PaddedSize to AllocSize, in the hope that this 2009-05-09 07:06:46 +00:00
CellSDKIntrinsics.td
CMakeLists.txt
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
README.txt CellSPU: 2009-01-21 04:58:48 +00:00
SPU64InstrInfo.td CellSPU: 2009-01-26 03:31:40 +00:00
SPU128InstrInfo.td CellSPU: 2009-01-21 04:58:48 +00:00
SPU.h Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00
SPU.td
SPUCallingConv.td CellSPU: 2009-01-06 23:10:38 +00:00
SPUFrameInfo.cpp
SPUFrameInfo.h
SPUHazardRecognizers.cpp Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUHazardRecognizers.h Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUInstrBuilder.h
SPUInstrFormats.td CellSPU: 2009-01-26 22:33:37 +00:00
SPUInstrInfo.cpp Change MachineInstrBuilder::addReg() to take a flag instead of a list of 2009-05-13 21:33:08 +00:00
SPUInstrInfo.h Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 2009-02-09 07:14:22 +00:00
SPUInstrInfo.td CellSPU: 2009-03-17 16:45:16 +00:00
SPUISelDAGToDAG.cpp CellSPU: 2009-03-17 16:45:16 +00:00
SPUISelLowering.cpp 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. 2009-04-27 18:41:29 +00:00
SPUISelLowering.h CellSPU: 2009-03-17 01:15:45 +00:00
SPUMachineFunction.h
SPUMathInstr.td Untabify code. 2009-01-26 03:37:41 +00:00
SPUNodes.td - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUOperands.td
SPURegisterInfo.cpp Propagate debug loc info through prologue/epilogue. 2009-02-23 00:42:30 +00:00
SPURegisterInfo.h Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 2009-02-06 17:43:24 +00:00
SPURegisterInfo.td CellSPU: 2009-01-06 23:10:38 +00:00
SPURegisterNames.h
SPUSchedule.td
SPUSubtarget.cpp
SPUSubtarget.h CellSPU: 2009-01-06 23:10:38 +00:00
SPUTargetAsmInfo.cpp CellSPU: 2009-01-26 22:33:37 +00:00
SPUTargetAsmInfo.h
SPUTargetMachine.cpp Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00
SPUTargetMachine.h Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: needed
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===