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3d6697fe50
As noted in the D44909 review, the transform from (fptosi+sitofp) to ftrunc
can produce -0.0 where the original code does not:
#include <stdio.h>
int main(int argc) {
float x;
x = -0.8 * argc;
printf("%f\n", (float)((int)x));
return 0;
}
$ clang -O0 -mavx fp.c ; ./a.out
0.000000
$ clang -O1 -mavx fp.c ; ./a.out
-0.000000
Ideally, we'd use IR/node flags to predicate the transform, but the IR parser
doesn't currently allow fast-math-flags on the cast instructions. So for now,
just use the function attribute that corresponds to clang's "-fno-signed-zeros"
option.
Differential Revision: https://reviews.llvm.org/D48085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335761 91177308-0d34-0410-b5e6-96231b3b80d8
234 lines
7.9 KiB
LLVM
234 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=sse4.1 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
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; PR37751 - https://bugs.llvm.org/show_bug.cgi?id=37751
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; We can't combine into 'round' instructions because the behavior is different for out-of-range values.
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declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
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declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)
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declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>)
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declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
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define float @float_to_int_to_float_mem_f32_i32(<4 x float>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_f32_i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttss2si (%rdi), %eax
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; SSE-NEXT: cvtsi2ssl %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_f32_i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttss2si (%rdi), %eax
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; AVX-NEXT: vcvtsi2ssl %eax, %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <4 x float>, <4 x float>* %p, align 16
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%fptosi = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %x)
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%sitofp = sitofp i32 %fptosi to float
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ret float %sitofp
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}
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define float @float_to_int_to_float_reg_f32_i32(<4 x float> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_f32_i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttss2si %xmm0, %eax
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: cvtsi2ssl %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_f32_i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttss2si %xmm0, %eax
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; AVX-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %x)
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%sitofp = sitofp i32 %fptosi to float
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ret float %sitofp
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}
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define float @float_to_int_to_float_mem_f32_i64(<4 x float>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_f32_i64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttss2si (%rdi), %rax
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; SSE-NEXT: cvtsi2ssq %rax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_f32_i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttss2si (%rdi), %rax
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; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <4 x float>, <4 x float>* %p, align 16
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%fptosi = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %x)
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%sitofp = sitofp i64 %fptosi to float
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ret float %sitofp
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}
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define float @float_to_int_to_float_reg_f32_i64(<4 x float> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_f32_i64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttss2si %xmm0, %rax
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: cvtsi2ssq %rax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_f32_i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttss2si %xmm0, %rax
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; AVX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %x)
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%sitofp = sitofp i64 %fptosi to float
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ret float %sitofp
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}
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define double @float_to_int_to_float_mem_f64_i32(<2 x double>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_f64_i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttsd2si (%rdi), %eax
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; SSE-NEXT: cvtsi2sdl %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_f64_i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttsd2si (%rdi), %eax
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; AVX-NEXT: vcvtsi2sdl %eax, %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <2 x double>, <2 x double>* %p, align 16
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%fptosi = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %x)
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%sitofp = sitofp i32 %fptosi to double
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ret double %sitofp
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}
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define double @float_to_int_to_float_reg_f64_i32(<2 x double> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_f64_i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttsd2si %xmm0, %eax
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: cvtsi2sdl %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_f64_i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttsd2si %xmm0, %eax
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; AVX-NEXT: vcvtsi2sdl %eax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %x)
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%sitofp = sitofp i32 %fptosi to double
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ret double %sitofp
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}
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define double @float_to_int_to_float_mem_f64_i64(<2 x double>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_f64_i64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttsd2si (%rdi), %rax
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; SSE-NEXT: cvtsi2sdq %rax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_f64_i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttsd2si (%rdi), %rax
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; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <2 x double>, <2 x double>* %p, align 16
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%fptosi = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %x)
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%sitofp = sitofp i64 %fptosi to double
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ret double %sitofp
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}
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define double @float_to_int_to_float_reg_f64_i64(<2 x double> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_f64_i64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttsd2si %xmm0, %rax
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: cvtsi2sdq %rax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_f64_i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttsd2si %xmm0, %rax
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; AVX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %x)
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%sitofp = sitofp i64 %fptosi to double
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ret double %sitofp
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}
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define <4 x float> @float_to_int_to_float_mem_v4f32(<4 x float>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttps2dq (%rdi), %xmm0
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttps2dq (%rdi), %xmm0
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <4 x float>, <4 x float>* %p, align 16
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x float>
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ret <4 x float> %sitofp
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}
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define <4 x float> @float_to_int_to_float_reg_v4f32(<4 x float> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttps2dq %xmm0, %xmm0
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x float>
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ret <4 x float> %sitofp
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}
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define <2 x double> @float_to_int_to_float_mem_v2f64(<2 x double>* %p) #0 {
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; SSE-LABEL: float_to_int_to_float_mem_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttpd2dq (%rdi), %xmm0
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttpd2dqx (%rdi), %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <2 x double>, <2 x double>* %p, align 16
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %x)
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%concat = shufflevector <4 x i32> %fptosi, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%sitofp = sitofp <2 x i32> %concat to <2 x double>
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ret <2 x double> %sitofp
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}
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define <2 x double> @float_to_int_to_float_reg_v2f64(<2 x double> %x) #0 {
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; SSE-LABEL: float_to_int_to_float_reg_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttpd2dq %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %x)
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%concat = shufflevector <4 x i32> %fptosi, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%sitofp = sitofp <2 x i32> %concat to <2 x double>
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ret <2 x double> %sitofp
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}
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attributes #0 = { "no-signed-zeros-fp-math"="true" }
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