llvm/test/CodeGen
Hal Finkel 75dd57a8f0 Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:

1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.

2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).

3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.

4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.

With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 03:39:34 +00:00
..
AArch64 AArch64: correct CodeGen of MOVZ/MOVK combinations. 2013-07-01 19:23:10 +00:00
ARM Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst") 2013-07-01 18:37:33 +00:00
CPP test commit: remove blank line. 2013-03-14 05:43:59 +00:00
Generic Debug Info: clean up usage of Verify. 2013-06-28 05:43:10 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs Revert "Adding DIImportedModules to DIScopes." 2013-03-28 02:44:59 +00:00
MBlaze Remove unnecessary leading comment characters in lit-only file 2013-03-18 22:08:16 +00:00
Mips [mips] Fix test case to check that mips64 instructions are generated. 2013-07-01 20:18:58 +00:00
MSP430 Really fix the test. Sorry for the breakage... 2013-07-01 19:51:36 +00:00
NVPTX [NVPTX] Add support for module-scope inline asm 2013-07-01 13:00:14 +00:00
PowerPC Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling 2013-07-02 03:39:34 +00:00
R600 R600: Support schedule and packetization of trans-only inst 2013-06-29 19:32:43 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
SystemZ [SystemZ] Fix some embarrassing test typos 2013-06-27 09:49:34 +00:00
Thumb LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
Thumb2 ARM: allow predicated barriers in Thumb mode 2013-06-26 16:52:32 +00:00
X86 Debug Info: clean up usage of Verify. 2013-06-28 05:43:10 +00:00
XCore [XCore] Fix handling of functions where only the LR is spilled. 2013-05-09 16:43:42 +00:00