Tim Northover 630c5e06d6 AArch64: use RegisterOperand for NEON registers. ... Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-13 07:26:52 +00:00
..
AArch64	AArch64: use RegisterOperand for NEON registers.	2013-09-13 07:26:52 +00:00
ARM	Somehow this important part of the patch, where I actually check the Mask,	2013-09-12 14:23:19 +00:00
AsmParser	Improve handling of .file, .include and .incbin directives to	2013-09-05 19:14:26 +00:00
COFF	Fix wrong code offset for unwind code SET_FPREG.	2013-08-27 04:16:16 +00:00
Disassembler	AArch64: use RegisterOperand for NEON registers.	2013-09-13 07:26:52 +00:00
ELF	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
MachO	Fixed a crash in the integrated assembler for Mach-O when a symbol difference	2013-09-05 20:25:06 +00:00
Markup
Mips	Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.	2013-09-10 09:50:01 +00:00
PowerPC	Implement asm support for a few PowerPC bookIII that are needed for assembling	2013-09-12 17:50:54 +00:00
SystemZ	[SystemZ] Add TM and TMY	2013-09-10 10:20:32 +00:00
X86	Partial support for Intel SHA Extensions (sha1rnds4)	2013-09-12 15:51:31 +00:00