llvm/test/MC
Ulrich Weigand 7c7c6b1c70 [SystemZ] Sort relocs to avoid code corruption by linker optimization
The SystemZ linkers provide an optimization to transform a general-
or local-dynamic TLS sequence into an initial-exec sequence if possible.
Do do that, the compiler generates a function call to __tls_get_offset,
which is a brasl instruction annotated with *two* relocations:

- a R_390_PLT32DBL to install __tls_get_offset as branch target
- a R_390_TLS_GDCALL / R_390_TLS_LDCALL to inform the linker that
  the TLS optimization should be performed if possible

If the optimization is performed, the brasl is replaced by an ld load
instruction.

However, *both* relocs are processed independently by the linker.
Therefore it is crucial that the R_390_PLT32DBL is processed *first*
(installing the branch target for the brasl) and the R_390_TLS_GDCALL
is processed *second* (replacing the whole brasl with an ld).

If the relocs are swapped, the linker will first replace the brasl
with an ld, and *then* install the __tls_get_offset branch target
offset.  Since ld has a different layout than brasl, this may even
result in a completely different (or invalid) instruction; in any
case, the resulting code is corrupted.

Unfortunately, the way the MC common code sorts relocations causes
these two to *always* end up the wrong way around, resulting in
wrong code generation by the linker and crashes.

This patch overrides the sortRelocs routine to detect this particular
pair of relocs and enforce the required order.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255787 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-16 18:12:40 +00:00
..
AArch64 [AArch64] Fix FP16 vector instructions that should only accept low registers 2015-12-09 14:32:11 +00:00
AMDGPU AMDGPU: Disallow flat_scr in SI assembler 2015-12-01 20:31:08 +00:00
ARM [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
AsmParser [MC] Use LShr for constant evaluation of ">>" on non-arm64 darwin. 2015-11-11 00:51:36 +00:00
COFF MC: Simplify handling of temporary symbols in COFF writer. 2015-11-26 23:29:27 +00:00
Disassembler [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
ELF [X86] Add relaxtion logic for SBB instructions. 2015-12-15 00:09:23 +00:00
Hexagon [Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings. 2015-12-03 21:44:28 +00:00
MachO [MC] Add a test for state reset in MCMachOStreamer 2015-12-05 01:02:53 +00:00
Markup
Mips [mips][ias] Range check uimm10 operands 2015-12-09 13:48:05 +00:00
PowerPC Relax a few more overspecified tests. 2015-11-03 19:38:19 +00:00
Sparc Update test to take into account for r251271. 2015-10-26 03:34:29 +00:00
SystemZ [SystemZ] Sort relocs to avoid code corruption by linker optimization 2015-12-16 18:12:40 +00:00
X86 I Added a triple flag for x86-evenDirective test. 2015-12-13 21:12:33 +00:00