Misha Brukman 8996f44f7a Fixed ordering of elements in instructions: although the binary instructions ... list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is instr rd, imm, rs1, and that is how they are constructed in the instruction selector. This fixes the discrepancy. Also fixed some comments along the same lines and fixed page numbers referring to where instructions are described in the Sparc manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8		2003-05-28 17:49:29 +00:00
..
CBackend	Add support for setjmp/longjmp primitives	2003-05-17 22:26:33 +00:00
SparcV9	Fixed ordering of elements in instructions: although the binary instructions	2003-05-28 17:49:29 +00:00
X86	Renamed opIsDef to opIsDefOnly.	2003-05-27 00:03:17 +00:00
Makefile	X86 target builds fine now	2002-11-20 20:17:03 +00:00
MRegisterInfo.cpp	Capture more information in ctor	2002-12-28 20:34:18 +00:00
TargetData.cpp	* Fix divide by zero error with empty structs	2003-05-21 18:08:44 +00:00
TargetInstrInfo.cpp	Rename MachineInstrInfo -> TargetInstrInfo	2003-01-14 22:00:31 +00:00
TargetMachine.cpp	The promotion rules are the same for all targets, they are set by the C standard.	2003-04-26 19:47:36 +00:00
TargetSchedInfo.cpp	More renamings of Target/Machine*Info to Target/Target*Info	2002-12-29 03:13:05 +00:00