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llvm/test/CodeGen/AMDGPU
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Nicolai Haehnle 318d6a2351 Add IntrWrite[Arg]Mem intrinsic property 
Summary:
This property is used to mark an intrinsic that only writes to memory, but
neither reads from memory nor has other side effects.

An example where this is useful is the llvm.amdgcn.buffer.store.format.*
intrinsic, which corresponds to a store instruction that goes through a special
buffer descriptor rather than through a plain pointer.

With this property, the intrinsic should still be handled as having side
effects at the LLVM IR level, but machine scheduling can make smarter
decisions.

Reviewers: tstellarAMD, arsenm, joker.eph, reames

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266826 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-19 21:58:33 +00:00
..
GlobalISel
AMDGPU: Add skeleton GlobalIsel implementation
2016-04-14 19:09:28 +00:00
32-bit-local-address-space.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
add_i64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
add-debug.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
add.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
address-space.ll
PeepholeOptimizer: Remove redundant copies
2015-09-25 20:22:12 +00:00
addrspacecast.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
amdgpu-shader-calling-convention.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
and-gcn.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
and.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
annotate-kernel-features-hsa.ll
AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr
2016-01-30 05:10:59 +00:00
annotate-kernel-features.ll
AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr
2016-01-30 05:10:59 +00:00
anyext.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
array-ptr-calc-i32.ll
AMDGPU: Enable LocalStackSlotAllocation pass
2016-04-16 02:13:37 +00:00
array-ptr-calc-i64.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
atomic_cmp_swap_local.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
atomic_load_add.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
atomic_load_sub.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
basic-branch.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
basic-loop.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
bfe_uint.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
bfi_int.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
bfm.ll
AMDGPU: Remove bfi and bfm intrinsics
2016-02-08 19:06:01 +00:00
big_alu.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
bitcast.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
bitreverse-inline-immediates.ll
AMDGPU: Materialize sign bits with bfrev
2016-03-11 07:42:49 +00:00
bitreverse.ll
AMDGPU: Use generic bitreverse intrinsic
2015-12-14 17:25:38 +00:00
branch-uniformity.ll
[DivergenceAnalysis] Treat PHI with incoming undef as constant
2016-04-14 17:42:47 +00:00
bswap.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
bug-vopc-commute.ll
AMDGPU: Guard VOPC instructions against incorrect commute
2016-04-19 21:58:22 +00:00
build_vector.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
call_fs.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
call.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
calling-conventions.ll
AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments()
2015-10-06 21:16:34 +00:00
captured-frame-index.ll
Add IntrWrite[Arg]Mem intrinsic property
2016-04-19 21:58:33 +00:00
cayman-loop-bug.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
cf_end.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
cf-stack-bug.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
cgp-addressing-modes-flat.ll
AMDGPU: Implement isNoopAddrSpaceCast
2015-12-01 23:04:00 +00:00
cgp-addressing-modes.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
cgp-bitfield-extract.ll
AMDGPU: Set HasExtractBitInsn
2016-03-01 04:58:17 +00:00
ci-use-flat-for-global.ll
AMDGPU: Set flat_scratch from flat_scratch_init reg
2016-02-12 06:31:30 +00:00
coalescer_distribute.ll
LiveInterval: Fix Distribute() failing on liveranges with unused VNInfos
2016-03-24 21:41:38 +00:00
coalescer_remat.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
codegen-prepare-addrmode-sext.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
combine_vloads.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
commute_modifiers.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
commute-compares.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
commute-shifts.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
complex-folding.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
concat_vectors.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
copy-illegal-type.ll
fix checks: *_DAG -> *-DAG
2016-03-28 22:11:06 +00:00
copy-to-reg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
ctlz_zero_undef.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ctlz.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ctpop64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ctpop.ll
AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions
2016-03-28 16:10:13 +00:00
cttz_zero_undef.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
cube.ll
AMDGPU: Add new amdgcn intrinsics for cube instructions
2016-01-26 04:29:56 +00:00
cvt_f32_ubyte.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
cvt_flr_i32_f32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
cvt_rpi_i32_f32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
dagcombine-reassociate-bug.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
debug.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
debugger_insert_nops.ll
[AMDGPU] Add insert nops pass based on subtarget features instead of cl::opt
2016-04-18 16:28:23 +00:00
default-fp-mode.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
disconnected-predset-break-bug.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
dot4-folding.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
drop-mem-operand-move-smrd.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
ds_read2_offset_order.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
ds_read2_superreg.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ds_read2.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
ds_read2st64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ds_write2.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
ds_write2st64.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
ds-sub-offset.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
dynamic_stackalloc.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
elf.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
elf.r600.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
empty-function.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
endcf-loop-header.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
extload-private.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
extload.ll
AMDGPU: Fix alignments in test
2016-02-22 21:04:23 +00:00
extract_vector_elt_i16.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
extract-vector-elt-i8.ll
AMDGPU: Make v32i8/v64i8 illegal types
2016-01-26 04:43:48 +00:00
extract-vector-elt-i64.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
extractelt-to-trunc.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
fabs.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fabs.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fadd64.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
fadd.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcanonicalize.ll
AMDGPU: Implement canonicalize
2016-04-14 01:42:16 +00:00
fceil64.ll
AMDGPU: Use s_addk_i32 / s_mulk_i32
2016-04-16 01:46:49 +00:00
fceil.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcmp64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcmp-cnd.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcmp-cnde-int-args.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcmp.ll
Fix CHECK directives that weren't checking.
2015-08-31 21:10:35 +00:00
fconst64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcopysign.f32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fcopysign.f64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
fdiv.f64.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fdiv.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fetch-limits.r600.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
fetch-limits.r700+.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
ffloor.f64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
ffloor.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
flat-address-space.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
flat-scratch-reg.ll
AMDGPU/SI: xnack_mask is always reserved on VI
2016-01-07 17:10:20 +00:00
floor.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
fma-combine.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fma.f64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fma.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
fmad.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
fmax3.f64.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fmax3.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fmax_legacy.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fmax_legacy.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fmax.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
fmaxnum.f64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fmaxnum.ll
AMDGPU: Materialize sign bits with bfrev
2016-03-11 07:42:49 +00:00
fmed3.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
fmin3.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fmin_legacy.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fmin_legacy.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fmin.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
fminnum.f64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fminnum.ll
AMDGPU: Materialize sign bits with bfrev
2016-03-11 07:42:49 +00:00
fmul64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fmul-2-combine-multi-use.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fmul.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fmuladd.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
fnearbyint.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fneg-fabs.f64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
fneg-fabs.ll
AMDGPU/SI: use S_OR for fneg (fabs f32)
2015-10-29 15:29:05 +00:00
fneg.f64.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
fneg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fp16_to_fp.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fp32_to_fp16.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fp_to_sint.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fp_to_sint.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fp_to_uint.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fp_to_uint.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fp-classify.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
fpext.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fptrunc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fract.f64.ll
AMDGPU: Remove AMDGPU.fract intrinsic
2016-01-22 18:42:38 +00:00
fract.ll
AMDGPU: Remove AMDGPU.fract intrinsic
2016-01-22 18:42:38 +00:00
frem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fsqrt.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
fsub64.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
fsub.ll
AMDGPU/SI: Fold operands with sub-registers
2016-01-07 17:10:29 +00:00
ftrunc.f64.ll
AMDGPU: Use s_addk_i32 / s_mulk_i32
2016-04-16 01:46:49 +00:00
ftrunc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
gep-address-space.ll
DAGCombiner: Combine extract_vector_elt from build_vector
2015-10-12 23:59:50 +00:00
global_atomics_i64.ll
AMDGPU: Implement i64 global atomics
2016-04-12 14:05:11 +00:00
global_atomics.ll
AMDGPU/SI: Implement atomic load/store for i32 and i64
2016-04-07 19:23:11 +00:00
global-constant.ll
AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA
2015-12-15 22:39:36 +00:00
global-directive.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
global-extload-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
global-extload-i8.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
global-extload-i16.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
global-extload-i32.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
global-zero-initializer.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
gv-const-addrspace-fail.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
gv-const-addrspace.ll
AMDGPU: don't match vgpr loads for constant loads
2015-07-27 18:16:08 +00:00
half.ll
DAGCombiner: Turn truncate of a bitcasted vector to an extract
2016-03-01 21:31:53 +00:00
hsa-default-device.ll
AMDGPU: Fix default device handling
2016-01-27 02:17:49 +00:00
hsa-fp-mode.ll
AMDGPU: Set DX10Clamp bit
2016-01-28 20:53:35 +00:00
hsa-globals.ll
[AMDGPU] Emit linkonce and linkonce_odr symbols
2016-04-05 16:00:58 +00:00
hsa-group-segment.ll
AMDGPU/SI: Don't emit group segment global variables
2015-12-02 17:00:42 +00:00
hsa-note-no-func.ll
AMDGPU/SI: Update ISA version for FIJI
2016-01-13 20:39:25 +00:00
hsa.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
i1-copy-implicit-def.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
i1-copy-phi.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
i8-to-double-to-float.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
icmp64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
icmp-select-sete-reverse-args.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
image-attributes.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
image-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
imm.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
indirect-addressing-si.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
indirect-private-64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
infinite-loop-evergreen.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
infinite-loop.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
inline-asm.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
inline-calls.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
inline-constraints.ll
AMDGPU/SI: Add support for sgpr and vgpr inline assembly constraints
2015-12-10 02:12:53 +00:00
input-mods.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
insert_subreg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
insert_vector_elt.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
invariant-load-no-alias-store.ll
DAGCombiner: Assume invariant load cannot alias a store
2015-07-10 22:17:40 +00:00
jump-address.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
kcache-fold.ll
AMDGPU: Replace some deprecated intrinsic uses in tests
2016-01-23 05:42:49 +00:00
kernel-args.ll
AMDGPU: Remove SIPrepareScratchRegs
2015-11-30 21:15:53 +00:00
large-alloca-compute.ll
AMDGPU: Set flat_scratch from flat_scratch_init reg
2016-02-12 06:31:30 +00:00
large-alloca-graphics.ll
AMDGPU/SI: Use the correct scratch wave offset register for shaders.
2016-04-14 16:27:03 +00:00
large-constant-initializer.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
large-work-group-promote-alloca.ll
AMDGPU: allow specifying a workgroup size that needs to fit in a compute unit
2016-04-14 16:27:07 +00:00
large-work-group-registers.ll
AMDGPU: allow specifying a workgroup size that needs to fit in a compute unit
2016-04-14 16:27:07 +00:00
lds-alignment.ll
AMDGPU: Account for LDS alignment
2016-02-05 19:47:29 +00:00
lds-initializer.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
lds-m0-init-in-loop.ll
AMDGPU: Add test for m0 initialization in basic loop
2016-04-13 00:39:52 +00:00
lds-oqap-crash.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lds-output-queue.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lds-size.ll
AMDGPU: Include LDS size in printed comment
2016-04-14 22:11:51 +00:00
lds-zero-initializer.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
legalizedag-bug-expand-setcc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lit.local.cfg
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
literals.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.amdgcn.atomic.dec.ll
AMDGPU: Add atomic_inc + atomic_dec intrinsics
2016-04-12 14:05:04 +00:00
llvm.amdgcn.atomic.inc.ll
AMDGPU: Add atomic_inc + atomic_dec intrinsics
2016-04-12 14:05:04 +00:00
llvm.amdgcn.buffer.atomic.ll
AMDGPU/SI: Fix regression with no-return atomics
2016-04-15 14:42:36 +00:00
llvm.amdgcn.buffer.load.format.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgcn.buffer.load.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
llvm.amdgcn.buffer.store.format.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
llvm.amdgcn.buffer.store.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Add cache invalidation instructions.
2015-09-24 19:52:21 +00:00
llvm.amdgcn.class.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
llvm.amdgcn.cos.ll
AMDGPU: Add intrinsics for sin/cos
2016-02-13 01:19:56 +00:00
llvm.amdgcn.cubeid.ll
AMDGPU: Add new amdgcn intrinsics for cube instructions
2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubema.ll
AMDGPU: Add new amdgcn intrinsics for cube instructions
2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubesc.ll
AMDGPU: Add new amdgcn intrinsics for cube instructions
2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubetc.ll
AMDGPU: Add new amdgcn intrinsics for cube instructions
2016-01-26 04:29:56 +00:00
llvm.amdgcn.dispatch.ptr.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
llvm.amdgcn.div.fixup.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.div.fmas.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
llvm.amdgcn.div.scale.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
llvm.amdgcn.ds.bpermute.ll
Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute"
2016-04-11 20:38:40 +00:00
llvm.amdgcn.ds.permute.ll
Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute"
2016-04-11 20:38:40 +00:00
llvm.amdgcn.frexp.exp.ll
AMDGPU: Add frexp_exp intrinsic
2016-03-30 22:28:52 +00:00
llvm.amdgcn.frexp.mant.ll
AMDGPU: Add frexp_mant intrinsic
2016-03-21 16:11:05 +00:00
llvm.amdgcn.groupstaticgroup.ll
AMDGPU/SI: Implement GroupStaticSize Intrinsic for Dynamic LDS
2016-03-15 17:28:44 +00:00
llvm.amdgcn.image.atomic.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgcn.image.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgcn.interp.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgcn.ldexp.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.log.clamp.ll
AMDGPU: Add intrinsics for sin/cos
2016-02-13 01:19:56 +00:00
llvm.amdgcn.mbcnt.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
2016-03-18 15:35:51 +00:00
llvm.amdgcn.rcp.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.read.workdim.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.rsq.clamp.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
llvm.amdgcn.rsq.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.s.barrier.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
llvm.amdgcn.s.dcache.inv.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll
AMDGPU: Add s_dcache_* instructions
2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.getreg.ll
AMDGPU/SI: Define S_GETREG Intrinsic
2016-03-10 16:47:15 +00:00
llvm.amdgcn.s.memrealtime.ll
AMDGPU: Implement readcyclecounter
2016-02-27 08:53:46 +00:00
llvm.amdgcn.s.memtime.ll
AMDGPU: Implement readcyclecounter
2016-02-27 08:53:46 +00:00
llvm.amdgcn.s.sleep.ll
AMDGPU: Add s_sleep intrinsic
2016-02-27 08:53:52 +00:00
llvm.amdgcn.sin.ll
AMDGPU: Add intrinsics for sin/cos
2016-02-13 01:19:56 +00:00
llvm.amdgcn.trig.preop.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.amdgcn.workgroup.id.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
llvm.amdgcn.workitem.id.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
llvm.AMDGPU.barrier.global.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.barrier.local.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.bfe.i32.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
llvm.AMDGPU.bfe.u32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.clamp.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.cube.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.AMDGPU.cvt_f32_ubyte.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.amdgpu.dp4.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.flbit.i32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.AMDGPU.kill.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.amdgpu.kilp.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.AMDGPU.rsq.clamped.f64.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
llvm.AMDGPU.rsq.clamped.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.AMDGPU.rsq.ll
AMDGPU: Restore AMDGPU prefixed rsq intrinsic for now
2016-01-26 04:14:16 +00:00
llvm.AMDGPU.tex.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.cos.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.dbg.value.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
llvm.exp2.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.log2.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.memcpy.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
llvm.pow.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.r600.read.local.size.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
llvm.r600.read.workdim.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
llvm.rint.f64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.rint.ll
AMDGPU: Remove AMDIL.round.nearest intrinsic
2016-01-20 21:05:40 +00:00
llvm.round.f64.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
llvm.round.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
llvm.SI.fs.interp.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.gather4.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.getlod.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.image.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.image.sample-masked.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.image.sample.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.image.sample.o.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.load.dword.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.packf16.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.sendmsg-m0.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.sendmsg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
llvm.SI.tbuffer.store.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.SI.tid.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.sin.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
llvm.sqrt.ll
DAGCombiner: Relax sqrt NaN folding check
2016-02-27 09:38:05 +00:00
load64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
load-input-fold.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
load.ll
AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions for HSA
2016-01-05 03:40:16 +00:00
load.vec.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
local-atomics64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
local-atomics.ll
AMDGPU: Add atomic_inc + atomic_dec intrinsics
2016-04-12 14:05:04 +00:00
local-memory-two-objects.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
local-memory.ll
AMDGPU: Rework how private buffer passed for HSA
2015-11-30 21:16:03 +00:00
loop-address.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
loop-idiom.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lower-range-metadata-intrinsic-call.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
lshl.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
lshr.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
m0-spill.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
mad_int24.ll
AMDGPU: Remove 24-bit intrinsics
2016-01-29 10:05:16 +00:00
mad_uint24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mad-combine.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
mad-sub.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
madak.ll
AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions
2016-03-28 16:10:13 +00:00
madmk.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
max3.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
max-literals.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
max.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
merge-stores.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
min3.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
min.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
missing-store.ll
AMDGPU/SI: Insert wait states required after v_readfirstlane on SI
2016-04-12 18:40:43 +00:00
move-addr64-rsrc-dead-subreg-writes.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
move-to-valu-atomicrmw.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
mubuf.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
mul_int24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
mul_uint24.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
mul.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
mulhu.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
multilevel-break.ll
AMDGPU/SI: Fix a mis-compilation of multi-level breaks
2016-04-12 16:10:38 +00:00
no-hsa-graphics-shaders.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
no-initializer-constant-addrspace.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
no-shrink-extloads.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
opencl-image-metadata.ll
AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass
2015-10-01 21:16:05 +00:00
operand-folding.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
operand-spacing.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
or.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
packetizer.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
parallelandifcollapse.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
parallelorifcollapse.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
partially-dead-super-register-immediate.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
predicate-dp4.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
predicates.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
private-element-size.ll
AMDGPU: More bits of frame index are known to be zero
2016-02-27 20:26:57 +00:00
private-memory-atomics.ll
AMDGPU: Do not promote allocas with non-inbounds GEPs
2016-02-02 21:16:12 +00:00
private-memory-broken.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
private-memory-r600.ll
AMDGPU: Do not promote allocas with non-inbounds GEPs
2016-02-02 21:16:12 +00:00
private-memory.ll
AMDGPU: Remove SignBitIsZero for mubuf scratch offsets
2016-03-21 18:02:18 +00:00
promote-alloca-bitcast-function.ll
Refactor backend diagnostics for unsupported features
2016-02-02 13:52:43 +00:00
promote-alloca-invariant-markers.ll
AMDGPU: Fix crash with invariant markers
2016-01-22 19:47:54 +00:00
promote-alloca-mem-intrinsics.ll
AMDGPU: Preserve alignments on new created globals
2016-02-05 19:47:23 +00:00
promote-alloca-no-opts.ll
AMDGPU: Skip promote alloca with no optimizations
2016-02-02 19:32:42 +00:00
promote-alloca-stored-pointer-value.ll
AMDGPU: Insert moves of frame index to value operands
2016-03-23 21:49:25 +00:00
promote-alloca-unhandled-intrinsic.ll
AMDGPU: Whitelist handled intrinsics
2016-02-02 19:18:53 +00:00
promote-alloca-volatile.ll
AMDGPU: Promote alloca should skip volatiles
2016-03-23 23:17:29 +00:00
pv-packing.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
pv.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
r600-encoding.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
r600-export-fix.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
r600cfg.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
rcp-pattern.ll
AMDGPU: Rename intrinsics to use amdgcn prefix
2016-01-22 21:30:34 +00:00
read_register.ll
AMDGPU: Implement read_register and write_register intrinsics
2016-01-26 04:29:24 +00:00
read-register-invalid-subtarget.ll
AMDGPU: Implement read_register and write_register intrinsics
2016-01-26 04:29:24 +00:00
read-register-invalid-type-i32.ll
AMDGPU: Implement read_register and write_register intrinsics
2016-01-26 04:29:24 +00:00
read-register-invalid-type-i64.ll
AMDGPU: Implement read_register and write_register intrinsics
2016-01-26 04:29:24 +00:00
readcyclecounter.ll
AMDGPU: Implement readcyclecounter
2016-02-27 08:53:46 +00:00
README
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
reciprocal.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
reg-coalescer-sched-crash.ll
RegisterCoalescer: Remap subregister lanemasks before exchanging operands
2016-03-05 04:36:13 +00:00
register-count-comments.ll
AMDGPU/SI: Use flat for global load/store when targeting HSA
2015-12-22 20:55:23 +00:00
reorder-stores.ll
AMDGPU: Make v2i64/v2f64 legal types.
2015-11-25 19:58:34 +00:00
ret_jump.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
ret.ll
AMDGPU/SI: Add latency for export instructions
2016-04-07 18:30:05 +00:00
rotl.i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotl.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotr.i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rotr.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
rsq.ll
AMDGPU: Add volatile to test loads and stores
2016-04-12 13:38:18 +00:00
rv7x0_count3.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
s_addk_i32.ll
AMDGPU: Use s_addk_i32 / s_mulk_i32
2016-04-16 01:46:49 +00:00
s_movk_i32.ll
AMDGPU: Reduce number of copies emitted
2015-09-24 07:16:37 +00:00
s_mulk_i32.ll
AMDGPU: Use s_addk_i32 / s_mulk_i32
2016-04-16 01:46:49 +00:00
saddo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
salu-to-valu.ll
[AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status
2016-04-13 16:18:41 +00:00
sampler-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
scalar_to_vector.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-fs-loop-nested-if.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
schedule-fs-loop-nested.ll
AMDGPU: Replace some deprecated intrinsic uses in tests
2016-01-23 05:42:49 +00:00
schedule-fs-loop.ll
AMDGPU: Replace some deprecated intrinsic uses in tests
2016-01-23 05:42:49 +00:00
schedule-global-loads.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
schedule-if-2.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-if.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
schedule-kernel-arg-loads.ll
AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions
2016-03-28 16:10:13 +00:00
schedule-vs-if-nested-loop-failure.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
schedule-vs-if-nested-loop.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
scratch-buffer.ll
AMDGPU: Remove SignBitIsZero for mubuf scratch offsets
2016-03-21 18:02:18 +00:00
sdiv.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sdivrem24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sdivrem64.ll
AMDGPU: Fold bitcasts of scalar constants to vectors
2016-04-14 21:58:07 +00:00
select64.ll
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
2015-09-09 15:43:26 +00:00
select-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
select-vectors.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
select.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-cnd.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-cnde-int.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-icmp-select-float.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc-opt.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
selectcc.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
set-dx10.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
setcc64.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
setcc-equivalent.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setcc-opt.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
setcc.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
seto.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
setuo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sext-eliminate.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sext-in-reg.ll
AMDGPU: Remove min/max intrinsics
2016-01-20 20:50:19 +00:00
sgpr-control-flow.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
sgpr-copy-duplicate-operand.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sgpr-copy.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
shared-op-cycle.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
shift-i64-opts.ll
AMDGPU: Reduce 64-bit SRAs
2016-01-18 22:09:04 +00:00
shl_add_constant.ll
AMDGPU: Use s_addk_i32 / s_mulk_i32
2016-04-16 01:46:49 +00:00
shl_add_ptr.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
shl.ll
AMDGPU: Split 64-bit and of constant up
2016-01-18 22:01:13 +00:00
si-annotate-cf-assertion.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
si-annotate-cf.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
si-annotate-cfg-loop-assert.ll
AMDGPU/SI: Annotate Loops with Constant Condition in SIAnnotateControlFlow pass.
2016-02-12 17:11:04 +00:00
si-instr-info-correct-implicit-operands.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
si-literal-folding.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
si-lod-bias.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
si-scheduler.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
si-sgpr-spill.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
si-spill-cf.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
si-spill-sgpr-stack.ll
AMDGPU/SI: Add support for spiling SGPRs to scratch buffer
2016-03-04 18:31:18 +00:00
si-triv-disjoint-mem-access.ll
Add IntrWrite[Arg]Mem intrinsic property
2016-04-19 21:58:33 +00:00
si-vector-hang.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sign_extend.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
simplify-demanded-bits-build-pair.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sint_to_fp.f64.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
sint_to_fp.i64.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
sint_to_fp.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
smed3.ll
AMDGPU: Match more med3 integer patterns
2016-03-07 21:54:48 +00:00
sminmax.ll
AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
2016-04-12 21:18:10 +00:00
smrd-vccz-bug.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
smrd.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
spill-alloc-sgpr-init-bug.ll
AMDGPU/SI: Do not move scratch resource register on Tonga & Iceland
2016-01-05 20:42:49 +00:00
spill-scavenge-offset.ll
AMDGPU: Quick fix for extreme slowness in spill-scavenge-offset.ll test
2016-02-12 00:05:34 +00:00
split-scalar-i64-add.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
split-smrd.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
split-vector-memoperand-offsets.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
sra.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
srem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
srl.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
ssubo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store_typed.ll
AMDGPU: Add MEM_RAT STORE_TYPED.
2015-10-01 17:51:34 +00:00
store-barrier.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
store-v3i32.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-v3i64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store-vector-ptrs.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
store.ll
AMDGPU/R600: Implement allowsMisalignedMemoryAccess
2016-02-22 21:04:16 +00:00
store.r600.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
structurize1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
structurize.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
sub.ll
AMDGPU: Add sdst operand to VOP2b instructions
2015-08-29 07:16:50 +00:00
subreg-coalescer-crash.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
subreg-coalescer-undef-use.ll
AMDGPU: Remove SIFixSGPRLiveRanges pass
2016-04-14 17:42:29 +00:00
subreg-eliminate-dead.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
swizzle-export.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
tex-clause-antidep.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
texture-input-merge.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
trunc-bitcast-vector.ll
DAGCombiner: Turn truncate of a bitcasted vector to an extract
2016-03-01 21:31:53 +00:00
trunc-cmp-constant.ll
AMDGPU/SI: Enable lanemask tracking in misched
2016-03-30 16:35:09 +00:00
trunc-store-f64-to-f16.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-store-i1.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc-store.ll
AMDGPU: Fix v16i32 to v16i8 truncstore
2015-07-31 04:12:04 +00:00
trunc-vector-store-assertion-failure.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
trunc.ll
AMDGPU/SI: use S_AND for i1 trunc
2015-10-29 15:05:03 +00:00
tti-unroll-prefs.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
uaddo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udiv.ll
AMDGPU: Cleanup udiv test
2016-01-11 21:18:40 +00:00
udivrem24.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udivrem64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
udivrem.ll
AMDGPU/SI: Improve MachineSchedModel definition
2016-03-30 16:35:13 +00:00
uint_to_fp.f64.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
uint_to_fp.i64.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
uint_to_fp.ll
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
2016-02-12 17:57:54 +00:00
umed3.ll
AMDGPU: Match more med3 integer patterns
2016-03-07 21:54:48 +00:00
unaligned-load-store.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unhandled-loop-condition-assertion.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
uniform-cfg.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
uniform-crash.ll
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
2016-02-12 23:45:29 +00:00
uniform-loop-inside-nonuniform.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
unroll.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
unsupported-cc.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
urecip.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
urem.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
use-sgpr-multiple-times.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
usubo.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
v1i64-kernel-arg.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
v_cndmask.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
v_mac.ll
AMDGPU: Run SIFoldOperands after PeepholeOptimizer
2016-04-14 21:58:24 +00:00
valu-i1.ll
CodeGen: Correct specification of PHI nodes
2016-03-28 18:18:41 +00:00
vector-alloca.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vertex-fetch-encoding.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vgpr-spill-emergency-stack-slot-compute.ll
AMDGPU: Prepare for reducing private element size.
2016-02-13 04:18:53 +00:00
vgpr-spill-emergency-stack-slot.ll
AMDGPU/SI: Use the correct scratch wave offset register for shaders.
2016-04-14 16:27:03 +00:00
vop-shrink.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
vselect64.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vselect.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
vtx-fetch-branch.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
vtx-schedule.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
wait.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
waitcnt-flat.ll
AMDGPU/SI: Fix s_waitcnt insertion for flat instructions
2016-02-19 15:33:13 +00:00
work-item-intrinsics.ll
AMDGPU: Add new amdgcn workitem intrinsics
2016-01-30 04:25:19 +00:00
wqm.ll
AMDGPU: Add a shader calling convention
2016-04-06 19:40:20 +00:00
write_register.ll
AMDGPU: Implement read_register and write_register intrinsics
2016-01-26 04:29:24 +00:00
write-register-vgpr-into-sgpr.ll
AMDGPU: Remove some old intrinsic uses from tests
2016-02-11 06:02:01 +00:00
wrong-transalu-pos-fix.ll
R600 -> AMDGPU rename
2015-06-13 03:28:10 +00:00
xor.ll
ScheduleDAGInstrs: Rework schedule graph builder.
2015-12-04 01:51:19 +00:00
zero_extend.ll
AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
2015-11-02 23:15:42 +00:00
zext-i64-bit-operand.ll
AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32
2016-04-12 18:24:38 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.
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