Jonas Paulsson 79d60f6e81 [SystemZ] Replicate the load with most uses in buildVector() ...

Iterate over all elements and count the number of uses among them for each
used load. Then make sure to REPLICATE the load which has the most uses in
order to minimize the number of needed element insertions.

Review: Ulrich Weigand
https://reviews.llvm.org/D54322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346637 91177308-0d34-0410-b5e6-96231b3b80d8

2018-11-12 08:12:20 +00:00

..

AArch64

[ARM64] [Windows] Handle funclets

2018-11-09 23:33:30 +00:00

AMDGPU

[AMDGPU] Cleanup optimize-if-exec-masking.mir test. NFC.

2018-11-09 18:23:39 +00:00

ARC

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ARM

[ARM] Add MemOperand to LDRcp to enable DCE.

2018-11-09 23:09:17 +00:00

AVR

[AVR] Reorder the CHECK lines in directmem.ll to match current trunk

2018-11-09 23:17:59 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

Workaround PPC backend bug in test for r346322.

2018-11-07 17:01:47 +00:00

Hexagon

[Hexagon] Implement noreturn optimization

2018-11-09 18:16:24 +00:00

Inputs

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Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars

2018-11-09 18:04:34 +00:00

MIR

[Power9] Allow gpr callee saved spills in prologue to vectors registers

2018-11-09 16:36:24 +00:00

MSP430

Revert "[MSP430] Add MC layer"

2018-11-08 16:21:29 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[Power9] Add support for stxvw4x.be and stxvd2x.be intrinsics

2018-11-05 17:31:26 +00:00

RISCV

[RISCV] Avoid unnecessary XOR for seteq/setne 0

2018-11-09 14:47:36 +00:00

SPARC

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00

SystemZ

[SystemZ] Replicate the load with most uses in buildVector()

2018-11-12 08:12:20 +00:00

Thumb

[SelectionDAG] swap select_cc operands to enable folding

2018-11-09 11:09:40 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Disable custom NaN payload tests

2018-11-09 22:04:37 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[x86] auto-generate complete checks; NFC

2018-11-11 14:57:26 +00:00

XCore

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00