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b5d50917ca
All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353061 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.1 KiB
LLVM
85 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- | FileCheck %s
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; Don't duplicate the load.
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define fastcc i32 @foo(i32* %p) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%ecx), %eax
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; CHECK-NEXT: andl $10, %eax
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb63
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_2: # %bb76
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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%t0 = load i32, i32* %p
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%t2 = and i32 %t0, 10
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%t3 = icmp ne i32 %t2, 0
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br i1 %t3, label %bb63, label %bb76
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bb63:
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ret i32 %t2
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bb76:
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ret i32 0
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}
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define fastcc double @bar(i32 %hash, double %x, double %y) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: andl $-8, %esp
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; CHECK-NEXT: fldl 16(%ebp)
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; CHECK-NEXT: fldl 8(%ebp)
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: andl $15, %eax
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; CHECK-NEXT: cmpl $8, %eax
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; CHECK-NEXT: jb .LBB1_2
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; CHECK-NEXT: # %bb.1: # %bb10
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; CHECK-NEXT: testb $1, %cl
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; CHECK-NEXT: je .LBB1_3
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; CHECK-NEXT: .LBB1_2: # %bb11
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; CHECK-NEXT: fchs
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; CHECK-NEXT: .LBB1_3: # %bb13
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; CHECK-NEXT: testb $2, %cl
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; CHECK-NEXT: je .LBB1_5
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; CHECK-NEXT: # %bb.4: # %bb14
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fchs
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: .LBB1_5: # %bb16
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; CHECK-NEXT: faddp %st, %st(1)
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; CHECK-NEXT: movl %ebp, %esp
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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entry:
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%0 = and i32 %hash, 15
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%1 = icmp ult i32 %0, 8
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br i1 %1, label %bb11, label %bb10
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bb10:
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%2 = and i32 %hash, 1
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%3 = icmp eq i32 %2, 0
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br i1 %3, label %bb13, label %bb11
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bb11:
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%4 = fsub double -0.000000e+00, %x
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br label %bb13
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bb13:
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%iftmp.9.0 = phi double [ %4, %bb11 ], [ %x, %bb10 ]
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%5 = and i32 %hash, 2
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%6 = icmp eq i32 %5, 0
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br i1 %6, label %bb16, label %bb14
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bb14:
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%7 = fsub double -0.000000e+00, %y
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br label %bb16
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bb16:
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%iftmp.10.0 = phi double [ %7, %bb14 ], [ %y, %bb13 ]
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%8 = fadd double %iftmp.9.0, %iftmp.10.0
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ret double %8
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}
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