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c8c80b0f2f
The machine scheduler currently biases register copies to/from physical registers to be closer to their point of use / def to minimize their live ranges. This change extends this to also physical register assignments from immediate values. This causes a reduction in reduction in overall register pressure and minor reduction in spills and indirectly fixes an out-of-registers assertion (PR39391). Most test changes are from minor instruction reorderings and register name selection changes and direct consequences of that. Reviewers: MatzeB, qcolombet, myatsina, pcc Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya, javed.absar, arphaman, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54218 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346894 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
4.7 KiB
LLVM
119 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
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; Trivial patchpoint codegen
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;
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define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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; CHECK-LABEL: trivial_patchpoint_codegen:
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; CHECK: movabsq $-559038736, %r11
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; CHECK-NEXT: callq *%r11
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: movq %rax, %[[REG:r.+]]
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; CHECK: callq *%r11
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: movq %[[REG]], %rax
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; CHECK: ret
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%resolveCall2 = inttoptr i64 -559038736 to i8*
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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%resolveCall3 = inttoptr i64 -559038737 to i8*
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
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ret i64 %result
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}
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; Trivial symbolic patchpoint codegen.
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;
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declare i64 @foo(i64 %p1, i64 %p2)
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define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) {
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entry:
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; CHECK-LABEL: trivial_symbolic_patchpoint_codegen:
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; CHECK: movabsq $_foo, %r11
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; CHECK-NEXT: callq *%r11
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: retq
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 15, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2)
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ret i64 %result
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}
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; Caller frame metadata with stackmaps. This should not be optimized
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; as a leaf function.
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;
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; CHECK-LABEL: caller_meta_leaf
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; CHECK: subq $32, %rsp
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; CHECK: Ltmp
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; CHECK: addq $32, %rsp
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; CHECK: ret
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define void @caller_meta_leaf() {
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entry:
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%metadata = alloca i64, i32 3, align 8
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store i64 11, i64* %metadata
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store i64 12, i64* %metadata
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store i64 13, i64* %metadata
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call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
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ret void
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}
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; Test patchpoints reusing the same TargetConstant.
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; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
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; There is no way to verify this, since it depends on memory allocation.
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; But I think it's useful to include as a working example.
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define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
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entry:
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%tmp80 = add i64 %tmp79, -16
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%tmp81 = inttoptr i64 %tmp80 to i64*
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%tmp82 = load i64, i64* %tmp81, align 8
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 5, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
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%tmp83 = load i64, i64* %tmp33, align 8
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%tmp84 = add i64 %tmp83, -24
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%tmp85 = inttoptr i64 %tmp84 to i64*
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%tmp86 = load i64, i64* %tmp85, align 8
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 5, i64 %arg, i64 %tmp10, i64 %tmp86)
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
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ret i64 10
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}
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; Test small patchpoints that don't emit calls.
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define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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; CHECK-LABEL: small_patchpoint_codegen:
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; CHECK: Ltmp
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; CHECK: nopl 8(%rax,%rax)
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; CHECK-NEXT: popq
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; CHECK-NEXT: ret
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
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ret void
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}
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; Test large target address.
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define i64 @large_target_address_patchpoint_codegen() {
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entry:
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; CHECK-LABEL: large_target_address_patchpoint_codegen:
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; CHECK: movabsq $6153737369414576827, %r11
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; CHECK-NEXT: callq *%r11
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%resolveCall2 = inttoptr i64 6153737369414576827 to i8*
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 0)
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ret i64 %result
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}
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declare i64 @consume_attributes(i64, i8* nest, i64)
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define i64 @test_patchpoint_with_attributes() {
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entry:
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; CHECK-LABEL: test_patchpoint_with_attributes:
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; CHECK: movl $42, %edi
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; CHECK: movl $17, %esi
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; CHECK: xorl %r10d, %r10d
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; CHECK: movabsq $_consume_attributes, %r11
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; CHECK-NEXT: callq *%r11
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: retq
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 21, i32 15, i8* bitcast (i64 (i64, i8*, i64)* @consume_attributes to i8*), i32 3, i64 42, i8* nest null, i64 17)
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ret i64 %result
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}
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declare void @llvm.experimental.stackmap(i64, i32, ...)
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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