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https://github.com/RPCS3/llvm.git
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939c183841
Original commit by Ayonam Ray. This commit adds a regression test for the issue discovered in the previous commit: that the range check for the jump table can only be omitted if the fall-through destination of the jump table is unreachable, which isn't necessarily true just because the default of the switch is unreachable. This addresses the missing optimization in PR41242. > During the lowering of a switch that would result in the generation of a > jump table, a range check is performed before indexing into the jump > table, for the switch value being outside the jump table range and a > conditional branch is inserted to jump to the default block. In case the > default block is unreachable, this conditional jump can be omitted. This > patch implements omitting this conditional branch for unreachable > defaults. > > Differential Revision: https://reviews.llvm.org/D52002 > Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357067 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
3.6 KiB
LLVM
93 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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%0 = type { %1 }
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%1 = type { %2 }
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%2 = type { %3 }
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%3 = type { %4 }
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%4 = type { %5 }
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%5 = type { i64, i64, i8* }
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%6 = type { %7, [23 x i8] }
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%7 = type { i8 }
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@.str.16 = external dso_local unnamed_addr constant [16 x i8], align 1
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@.str.17 = external dso_local unnamed_addr constant [12 x i8], align 1
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@.str.18 = external dso_local unnamed_addr constant [15 x i8], align 1
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #0
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define void @pr38743(i32 %a0) #1 align 2 {
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; CHECK-LABEL: pr38743:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: decl %edi
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; CHECK-NEXT: jmpq *.LJTI0_0(,%rdi,8)
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; CHECK-NEXT: .LBB0_2: # %bb5
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; CHECK-NEXT: movzwl .str.17+{{.*}}(%rip), %eax
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; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq {{.*}}(%rip), %rax
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; CHECK-NEXT: jmp .LBB0_4
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; CHECK-NEXT: .LBB0_1: # %bb2
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; CHECK-NEXT: movq .str.16+{{.*}}(%rip), %rax
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq {{.*}}(%rip), %rax
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; CHECK-NEXT: jmp .LBB0_4
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; CHECK-NEXT: .LBB0_3: # %bb8
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; CHECK-NEXT: movq .str.18+{{.*}}(%rip), %rax
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq {{.*}}(%rip), %rax
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; CHECK-NEXT: .LBB0_4: # %bb12
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq %rax, (%rax)
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; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %al
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
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; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi
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; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %dil
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; CHECK-NEXT: movb %al, (%rax)
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; CHECK-NEXT: movq %rcx, 1(%rax)
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; CHECK-NEXT: movw %dx, 9(%rax)
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; CHECK-NEXT: movl %esi, 11(%rax)
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; CHECK-NEXT: movb %dil, 15(%rax)
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; CHECK-NEXT: retq
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bb:
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%tmp = alloca %0, align 16
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%tmp1 = bitcast %0* %tmp to i8*
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switch i32 %a0, label %bb11 [
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i32 1, label %bb2
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i32 4, label %bb5
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i32 2, label %bb5
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i32 3, label %bb8
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]
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bb2: ; preds = %bb
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%tmp3 = bitcast %0* %tmp to %6*
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%tmp4 = getelementptr inbounds %6, %6* %tmp3, i64 0, i32 1, i64 0
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 %tmp4, i8* align 1 getelementptr inbounds ([16 x i8], [16 x i8]* @.str.16, i64 0, i64 0), i64 15, i1 false)
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br label %bb12
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bb5: ; preds = %bb, %bb
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%tmp6 = bitcast %0* %tmp to %6*
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%tmp7 = getelementptr inbounds %6, %6* %tmp6, i64 0, i32 1, i64 0
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 %tmp7, i8* align 1 getelementptr inbounds ([12 x i8], [12 x i8]* @.str.17, i64 0, i64 0), i64 10, i1 false)
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br label %bb12
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bb8: ; preds = %bb
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%tmp9 = bitcast %0* %tmp to %6*
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%tmp10 = getelementptr inbounds %6, %6* %tmp9, i64 0, i32 1, i64 0
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 %tmp10, i8* align 1 getelementptr inbounds ([15 x i8], [15 x i8]* @.str.18, i64 0, i64 0), i64 14, i1 false)
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br label %bb12
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bb11: ; preds = %bb
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unreachable
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bb12: ; preds = %bb8, %bb5, %bb2
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 8 undef, i8* nonnull align 16 %tmp1, i64 24, i1 false) #2
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ret void
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}
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { "target-features"="+sse,+sse2,+sse3,+sse4.2" }
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attributes #2 = { nounwind }
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