llvm/MC at a942d77488f2fddaa55937bf53640ea7ffdab98b - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-03-04 16:47:41 +00:00

History

Matt Arsenault 8d631491b3 AMDGPU: Fix handling of 16-bit immediates

Since 32-bit instructions with 32-bit input immediate behavior
are used to materialize 16-bit constants in 32-bit registers
for 16-bit instructions, determining the legality based
on the size is incorrect. Change operands to have the size
specified in the type.

Also adds a workaround for a disassembler bug that
produces an immediate MCOperand for an operand that
is supposed to be OPERAND_REGISTER.

The assembler appears to accept out of bounds immediates and
truncates them, but this seems to be an issue for 32-bit
already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289306 91177308-0d34-0410-b5e6-96231b3b80d8

2016-12-10 00:39:12 +00:00

AArch64

[AArch64] Refactor LSE support as feature separate from V8.1a support.

2016-11-30 22:25:24 +00:00

AMDGPU

AMDGPU: Fix handling of 16-bit immediates

2016-12-10 00:39:12 +00:00

ARM

[ARM] Better error message for invalid flag-preserving Thumb1 insts

2016-12-06 12:59:08 +00:00

AsmParser

[AsmParser] Diagnose empty symbol for .set directive