* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
+==============================================================================+
| How to organize the lit tests |
+==============================================================================+
- If you write a test for matching a single DAG opcode or intrinsic, it should
go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)
- If you write a test that matches several DAG opcodes and checks for a single
ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
bfi_int.ll
- For all other tests, use your best judgement for organizing tests and naming
the files.
+==============================================================================+
| Naming conventions |
+==============================================================================+
- Use dash '-' and not underscore '_' to separate words in file names, unless
the file is named after a DAG opcode or ISA instruction that has an
underscore '_' in its name.
Tom Stellard
692ee102eb