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llvm/lib/Target/R600
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Bill Wendling b5632b5b45 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
..
InstPrinter Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 2013-05-23 17:10:37 +00:00
MCTargetDesc R600: Hide symbols of implementation details. 2013-05-23 15:43:05 +00:00
TargetInfo R600: Remove unnecessary include 2013-06-07 20:28:43 +00:00
AMDGPU.h R600: Remove unnecessary include 2013-06-07 20:28:43 +00:00
AMDGPU.td R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
AMDGPUAsmPrinter.cpp Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 2013-05-23 17:10:37 +00:00
AMDGPUAsmPrinter.h R600: Emit used GPRs count 2013-04-17 15:17:25 +00:00
AMDGPUCallingConv.td R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp R600: Support for indirect addressing v4 2013-02-06 17:32:29 +00:00
AMDGPUFrameLowering.h R600: Support for indirect addressing v4 2013-02-06 17:32:29 +00:00
AMDGPUIndirectAddressing.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
AMDGPUInstrInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
AMDGPUInstrInfo.h R600: Support for indirect addressing v4 2013-02-06 17:32:29 +00:00
AMDGPUInstrInfo.td Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend. 2013-05-22 06:36:09 +00:00
AMDGPUInstructions.td R600/SI: Add support for global loads 2013-06-03 17:39:43 +00:00
AMDGPUIntrinsics.td R600/SI: remove shader type intrinsic 2013-03-07 09:03:46 +00:00
AMDGPUISelLowering.cpp R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
AMDGPUISelLowering.h R600/SI: Add support for work item and work group intrinsics 2013-06-03 17:40:18 +00:00
AMDGPUMachineFunction.cpp R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 2013-04-26 18:32:24 +00:00
AMDGPUMachineFunction.h R600/SI: Share code recording ShaderTypeAttribute between generations 2013-04-01 21:47:53 +00:00
AMDGPUMCInstLower.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
AMDGPUMCInstLower.h R600: BB operand support for SI 2012-12-17 15:14:54 +00:00
AMDGPURegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.td Make SubRegIndex size mandatory, following r183020. 2013-05-31 23:45:26 +00:00
AMDGPUStructurizeCFG.cpp Silencing an MSVC warning about mixing bool and unsigned int. 2013-06-04 01:03:03 +00:00
AMDGPUSubtarget.cpp R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
AMDGPUSubtarget.h R600: Factorize Fetch size limit inside AMDGPUSubTarget 2013-05-17 16:49:55 +00:00
AMDGPUTargetMachine.cpp R600: Add a pass that merge Vector Register 2013-06-05 21:38:04 +00:00
AMDGPUTargetMachine.h Fix a leak on the r600 backend. 2013-05-23 03:31:47 +00:00
AMDIL7XXDevice.cpp
AMDIL7XXDevice.h
AMDIL.h R600/SI: remove SGPR address space v2 2013-03-07 09:03:59 +00:00
AMDILBase.td R600: Move Subtarget feature definitions into AMDGPU.td 2013-06-07 20:28:49 +00:00
AMDILCFGStructurizer.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
AMDILDevice.cpp R600: Clean up datalayout strings so they better match hardware capabilities 2013-03-04 17:40:28 +00:00
AMDILDevice.h Remove redundant 'llvm::' qualifications 2013-01-13 16:01:15 +00:00
AMDILDeviceInfo.cpp R600/SI: Add processor type for Hainan asic 2013-05-14 14:42:56 +00:00
AMDILDeviceInfo.h R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
AMDILDevices.h
AMDILEvergreenDevice.cpp
AMDILEvergreenDevice.h Resort the #include lines in include/... and lib/... with the 2013-01-02 10:22:59 +00:00
AMDILInstrInfo.td R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern 2013-02-18 14:11:28 +00:00
AMDILIntrinsicInfo.cpp Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER. 2013-05-22 14:57:42 +00:00
AMDILIntrinsicInfo.h Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
AMDILIntrinsics.td R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern 2013-02-18 14:11:28 +00:00
AMDILISelDAGToDAG.cpp Cast to the proper type. 2013-06-06 01:04:21 +00:00
AMDILISelLowering.cpp Track IR ordering of SelectionDAG nodes 2/4. 2013-05-25 02:42:55 +00:00
AMDILNIDevice.cpp Resort the #include lines in include/... and lib/... with the 2013-01-02 10:22:59 +00:00
AMDILNIDevice.h Resort the #include lines in include/... and lib/... with the 2013-01-02 10:22:59 +00:00
AMDILRegisterInfo.td
AMDILSIDevice.cpp R600: Clean up datalayout strings so they better match hardware capabilities 2013-03-04 17:40:28 +00:00
AMDILSIDevice.h
CMakeLists.txt R600: Add a pass that merge Vector Register 2013-06-05 21:38:04 +00:00
LLVMBuild.txt
Makefile
Processors.td R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
R600ControlFlowFinalizer.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600Defines.h R600: Relax some vector constraints on Dot4. 2013-05-17 16:50:32 +00:00
R600EmitClauseMarkers.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600ExpandSpecialInstrs.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600InstrInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600InstrInfo.h R600: Const/Neg/Abs can be folded to dot4 2013-06-04 23:17:15 +00:00
R600Instructions.td R600: Constraints input regs of interp_xy,_zw 2013-06-03 15:44:16 +00:00
R600Intrinsics.td R600: Improve texture handling 2013-05-17 16:50:20 +00:00
R600ISelLowering.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600ISelLowering.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600MachineFunctionInfo.cpp R600/SI: Share code recording ShaderTypeAttribute between generations 2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 2013-05-23 17:10:37 +00:00
R600MachineScheduler.cpp R600: Remove leftover code in R600MachineScheduler.cpp 2013-06-06 14:18:29 +00:00
R600MachineScheduler.h R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
R600OptimizeVectorRegisters.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600Packetizer.cpp R600: 3 op instructions have no write bit but the result are store in PV 2013-06-03 15:56:12 +00:00
R600RegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600RegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
R600RegisterInfo.td R600: use capital letter for PV channel 2013-06-03 15:44:35 +00:00
R600Schedule.td R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 2013-04-30 00:14:17 +00:00
R600TextureIntrinsicsReplacer.cpp Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 2013-05-23 17:10:37 +00:00
SIAnnotateControlFlow.cpp R600: Remove unnecessary include 2013-06-07 20:28:43 +00:00
SIDefines.h R600/SI: Emit config values in register value pairs. 2013-04-15 17:51:35 +00:00
SIInsertWaits.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIInstrFormats.td R600/SI: Use the same names for VOP3 operands and encoding fields 2013-05-20 15:02:08 +00:00
SIInstrInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIInstrInfo.h R600/SI: adjust writemask to only the used components 2013-04-10 08:39:08 +00:00
SIInstrInfo.td Cast to the correct type. Pointer, not reference. 2013-06-06 05:39:29 +00:00
SIInstructions.td R600/SI: Add support for global loads 2013-06-03 17:39:43 +00:00
SIIntrinsics.td R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode 2013-05-06 23:02:19 +00:00
SIISelLowering.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIISelLowering.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SILowerControlFlow.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIMachineFunctionInfo.cpp R600/SI: Share code recording ShaderTypeAttribute between generations 2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h R600/SI: Share code recording ShaderTypeAttribute between generations 2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIRegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:28:55 +00:00
SIRegisterInfo.td R600/SI: dynamical figure out the reg class of MIMG 2013-04-10 08:39:16 +00:00
SISchedule.td