llvm/test/CodeGen/PowerPC/2012-10-12-bitcast.ll
Bill Schmidt 551a3d7b56 [PowerPC] Clean up -mattr=+vsx tests to always specify -mcpu
We recently discovered an issue that reinforces what a good idea it is
to always specify -mcpu in our code generation tests, particularly for
-mattr=+vsx.  This patch ensures that all tests that specify
-mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate.

Some of the uses of -mattr=+vsx added recently don't make much sense
(when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32,
for example).  For cases like this I've just removed the extra VSX
test commands; there's enough coverage without them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-19 21:29:21 +00:00

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LLVM

; RUN: llc -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i32 @test(<16 x i8> %v) nounwind {
entry:
%0 = bitcast <16 x i8> %v to i128
%1 = lshr i128 %0, 96
%2 = trunc i128 %1 to i32
ret i32 %2
}
; Verify that bitcast handles big-endian platforms correctly
; by checking we load the result from the correct offset
; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
; CHECK: stvx 2, 0, [[REGISTER]]
; CHECK: lwz 3, -16(1)
; CHECK: blr
; CHECK-VSX: addi [[REGISTER:[0-9]+]], 1, -16
; CHECK-VSX: stxvd2x 34, 0, [[REGISTER]]
; CHECK-VSX: lwz 3, -16(1)
; CHECK-VSX: blr