Juergen Ributzka 5d6365c80c [FastISel][AArch64] Use the correct register class to make the MI verifier happy. ... This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-21 20:57:57 +00:00
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AArch64	[FastISel][AArch64] Use the correct register class to make the MI verifier happy.	2014-08-21 20:57:57 +00:00
ARM	Add a thread-model knob for lowering atomics on baremetal & single threaded systems	2014-08-21 14:35:47 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Fix fmul combines with constant splat vectors	2014-08-16 10:14:19 +00:00
MSP430
NVPTX
PowerPC	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
R600	R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions	2014-08-21 20:41:00 +00:00
SPARC
SystemZ
Thumb	Thumb1 load/store optimizer: Improve code to materialize new base register.	2014-08-21 17:11:03 +00:00
Thumb2	[ARM] Enable DP copy, load and store instructions for FPv4-SP	2014-08-21 12:50:31 +00:00
X86	DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.	2014-08-21 13:28:02 +00:00
XCore