Silviu Baranga fa1ebc6abe Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8

2012-04-18 13:12:50 +00:00

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arm-tests.txt

Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.

2012-04-18 13:02:55 +00:00

basic-arm-instructions.txt

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fp-encoding.txt

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invalid-Bcc-thumb.txt

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invalid-BFI-arm.txt

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invalid-CPS2p-arm.txt

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invalid-CPS3p-arm.txt

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invalid-DMB-thumb.txt

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invalid-DSB-arm.txt

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invalid-IT-CBNZ-thumb.txt

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invalid-IT-CC15.txt

Change ARMInstPrinter::printPredicateOperand() so it will not abort if it

2012-03-01 22:13:02 +00:00

invalid-IT-thumb.txt

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invalid-LDC-form-arm.txt

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invalid-LDM-thumb.txt

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invalid-LDR_POST-arm.txt

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invalid-LDR_PRE-arm.txt

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invalid-LDRB_POST-arm.txt

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invalid-LDRD_PRE-thumb.txt

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invalid-LDRrs-arm.txt

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invalid-MCR-arm.txt

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invalid-MOVr-arm.txt

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invalid-MOVs-arm.txt

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invalid-MOVs-LSL-arm.txt

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invalid-MOVTi16-arm.txt

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invalid-MRRC2-arm.txt

Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

2012-04-18 13:12:50 +00:00

invalid-MSRi-arm.txt

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invalid-RFEorLDMIA-arm.txt

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invalid-SBFX-arm.txt

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invalid-SMLAD-arm.txt

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invalid-SRS-arm.txt

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invalid-STMIA_UPD-thumb.txt

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invalid-SXTB-arm.txt

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invalid-t2Bcc-thumb.txt

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invalid-t2LDRBT-thumb.txt

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invalid-t2LDREXD-thumb.txt

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invalid-t2LDRSHi8-thumb.txt

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invalid-t2LDRSHi12-thumb.txt

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invalid-t2PUSH-thumb.txt

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invalid-t2STR_POST-thumb.txt

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invalid-t2STRD_PRE-thumb.txt

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invalid-t2STREXB-thumb.txt

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invalid-t2STREXD-thumb.txt

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invalid-UMAAL-arm.txt

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invalid-VLD1DUPq8_UPD-arm.txt

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invalid-VLD3DUPd32_UPD-thumb.txt

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invalid-VLDMSDB_UPD-arm.txt

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invalid-VQADD-arm.txt

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invalid-VST1d8Twb_register-thumb.txt

Fixed a case of ARM disassembly getting an assert on a bad encoding

2012-04-11 22:40:17 +00:00

invalid-VST2b32_UPD-arm.txt

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ldrd-armv4.txt

Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.

2012-04-02 15:20:39 +00:00

lit.local.cfg

Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu

2012-03-25 09:02:19 +00:00

memory-arm-instructions.txt

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neon-tests.txt

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neon.txt

Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)

2012-04-17 00:49:27 +00:00

neont2.txt

Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)

2012-04-17 00:49:27 +00:00

thumb1.txt

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thumb2.txt

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thumb-MSR-MClass.txt

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thumb-printf.txt

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thumb-tests.txt

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unpredictable-ADC-arm.txt

Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.

2012-04-05 16:19:29 +00:00

unpredictable-ADDREXT3-arm.txt

Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.

2012-03-22 14:14:49 +00:00

unpredictable-AI1cmp-arm.txt

Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.

2012-04-18 12:48:43 +00:00

unpredictable-LDR-arm.txt

Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM

2012-03-22 13:24:43 +00:00

unpredictable-LDRD-arm.txt

Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.

2012-03-22 14:14:49 +00:00

unpredictable-LSL-regform.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-MRRC2-arm.txt

Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

2012-04-18 13:12:50 +00:00

unpredictable-MUL-arm.txt

Added soft fail cases for the disassembler when decoding MUL instructions on ARM.

2012-03-22 13:14:39 +00:00

unpredictable-RSC-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-SHADD16-arm.txt

Added support for handling unpredictable arithmetic instructions on ARM.

2012-04-05 16:13:15 +00:00

unpredictable-SSAT-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-STRBrs-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-UQADD8-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictables-thumb.txt

Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.

2012-02-09 10:56:31 +00:00

vfp4.txt

Fix a number of problems with ARM fused multiply add/subtract instructions.

2012-04-11 00:13:00 +00:00