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fce447566a
Summary: This patch transforms the Scheduler class into the ExecuteStage. Most of the logic remains. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47246 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334679 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
4.2 KiB
C++
112 lines
4.2 KiB
C++
//===----------------------- DispatchStage.h --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file models the dispatch component of an instruction pipeline.
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///
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/// The DispatchStage is responsible for updating instruction dependencies
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/// and communicating to the simulated instruction scheduler that an instruction
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/// is ready to be scheduled for execution.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
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#define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
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#include "Instruction.h"
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#include "RegisterFile.h"
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#include "RetireControlUnit.h"
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#include "Stage.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace mca {
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class WriteState;
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class Scheduler;
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class Backend;
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// Implements the hardware dispatch logic.
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//
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// This class is responsible for the dispatch stage, in which instructions are
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// dispatched in groups to the Scheduler. An instruction can be dispatched if
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// functional units are available.
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// To be more specific, an instruction can be dispatched to the Scheduler if:
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// 1) There are enough entries in the reorder buffer (implemented by class
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// RetireControlUnit) to accommodate all opcodes.
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// 2) There are enough temporaries to rename output register operands.
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// 3) There are enough entries available in the used buffered resource(s).
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//
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// The number of micro opcodes that can be dispatched in one cycle is limited by
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// the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when
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// processor resources are not available (i.e. at least one of the
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// aforementioned checks fails). Dispatch stall events are counted during the
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// entire execution of the code, and displayed by the performance report when
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// flag '-verbose' is specified.
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//
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// If the number of micro opcodes of an instruction is bigger than
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// DispatchWidth, then it can only be dispatched at the beginning of one cycle.
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// The DispatchStage will still have to wait for a number of cycles (depending
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// on the DispatchWidth and the number of micro opcodes) before it can serve
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// other instructions.
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class DispatchStage : public Stage {
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unsigned DispatchWidth;
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unsigned AvailableEntries;
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unsigned CarryOver;
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Backend *Owner;
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const llvm::MCSubtargetInfo &STI;
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RetireControlUnit &RCU;
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RegisterFile &PRF;
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Scheduler ≻
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bool checkRCU(const InstRef &IR);
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bool checkPRF(const InstRef &IR);
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bool checkScheduler(const InstRef &IR);
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void dispatch(InstRef IR);
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bool isRCUEmpty() const { return RCU.isEmpty(); }
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void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
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void notifyInstructionDispatched(const InstRef &IR,
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llvm::ArrayRef<unsigned> UsedPhysRegs);
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bool isAvailable(unsigned NumEntries) const {
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return NumEntries <= AvailableEntries || AvailableEntries == DispatchWidth;
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}
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bool canDispatch(const InstRef &IR) {
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assert(isAvailable(IR.getInstruction()->getDesc().NumMicroOps));
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return checkRCU(IR) && checkPRF(IR) && checkScheduler(IR);
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}
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void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
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unsigned RegID) const {
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return PRF.collectWrites(Vec, RegID);
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}
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public:
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DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
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unsigned MaxDispatchWidth, RetireControlUnit &R,
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RegisterFile &F, Scheduler &Sched)
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: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
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CarryOver(0U), Owner(B), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
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virtual bool isReady() const override final { return isRCUEmpty(); }
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virtual void preExecute(const InstRef &IR) override final;
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virtual bool execute(InstRef &IR) override final;
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void notifyDispatchStall(const InstRef &IR, unsigned EventType);
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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} // namespace mca
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#endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
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