rsx: Fix flush predictor behavior when using surface cache targets for blit engine

This commit is contained in:
kd-11
2026-09-17 21:42:07 +03:00
committed by kd-11
parent e76fbf4489
commit a90c841b39
4 changed files with 11 additions and 15 deletions
+6 -4
View File
@@ -1829,6 +1829,7 @@ namespace rsx
// Fake RTT cache hit
dst_subres.surface = dst_surface;
dst_subres.base_address = section_attr.address;
dst_is_render_target = true;
dest_texture = dst_surface->get_surface(rsx::surface_access::transfer_write);
@@ -3798,16 +3799,17 @@ namespace rsx
if (cached_dest)
{
result.real_dst_address = cached_dest->get_section_base();
result.real_dst_size = cached_dest->get_section_size();
result.dst_range = utils::address_range32::start_length(
cached_dest->get_section_base(),
cached_dest->get_section_size());
}
else
{
ensure(dst_is_render_target);
dst_subres.surface->on_write_copy(rsx::get_shared_tag(), false, raster_type);
result.real_dst_address = dst_base_address;
result.real_dst_size = dst.pitch * dst_dimensions.height;
// We use the full surface range here. Blit resources are always locked after writing regardless of WCB/WDB settings.
result.dst_range = dst_subres.surface->get_memory_range();
}
return result;
+1 -7
View File
@@ -49,16 +49,10 @@ namespace rsx
struct blit_op_result
{
bool succeeded = false;
u32 real_dst_address = 0;
u32 real_dst_size = 0;
utils::address_range32 dst_range{};
blit_op_result(bool success) : succeeded(success)
{}
inline address_range32 to_address_range() const
{
return address_range32::start_length(real_dst_address, real_dst_size);
}
};
struct blit_target_properties
+2 -2
View File
@@ -945,9 +945,9 @@ namespace gl
if (result.succeeded)
{
if (result.real_dst_size)
if (result.dst_range.valid())
{
flush_if_cache_miss_likely(cmd, result.to_address_range());
flush_if_cache_miss_likely(cmd, result.dst_range);
}
return true;
+2 -2
View File
@@ -1686,9 +1686,9 @@ namespace vk
if (reply.succeeded)
{
if (reply.real_dst_size)
if (reply.dst_range.valid())
{
flush_if_cache_miss_likely(cmd, reply.to_address_range());
flush_if_cache_miss_likely(cmd, reply.dst_range);
}
return true;