RPCS3/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2026-10-11 22:49:55 +00:00
Code Issues Packages Projects Releases Wiki Activity
20,268 Commits 9 Branches 78 Tags
52343fa2f39ca628b40a618a0082a9cff883a286
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Malcolm 52343fa2f3 BufferUtils: Add native NEON upload paths 2026-10-10 12:40:20 +03:00
Whatcookie 1b90d1c149 rsx: Optimize recursion in the vertex program analyzer's instruction walk 
Avoid use of std::function for recursion, and ensure that std::stack is backed by a vector, instead of the default deque.
 2026-10-06 10:00:59 +00:00
Malcolm 183597deea RSX: use cache-line waits for event queue draining 2026-10-06 09:03:01 +02:00
Malcolm f0d2485981 CMake: Add LSE2 option 2026-09-30 13:46:49 +03:00
Malcolm be39b3b9f0 atomic: Detect LSE2 at runtime on ARM64 2026-09-30 13:46:49 +03:00
Malcolmandjpolo1224 e13ee15791 SPU LLVM: Stop inverting float-to-int saturation on ARM64 
- Fix CFLTS saturation in the approximate and accurate xfloat paths
- Original fix credit to jpolo1224 of armsx3 https://github.com/ARMSX2/ARMSX3/commit/424514fde67adb83540d39feea860b5eb17b3500
- Accurate-xfloat follow-up https://github.com/ARMSX2/ARMSX3/commit/19d23eb6913c34cb63c00861bf95e58c3144e78e

Co-authored-by: jpolo1224 <[email protected]>
 2026-09-16 14:04:34 +03:00
Malcolm e826098bcb SPU LLVM: Omit test_state and spu-null if they are unreachable 2026-09-16 09:28:19 +03:00
Malcolm ec4b1ae655 SPU LLVM: Use TBL for ARM64 byteswaps 2026-09-15 10:50:56 +03:00
Malcolm 41f0ecc17b SPU LLVM: Ifdef some code to be x86 only 
- might speedup arm via avoiding some x86 optimizations that don't use intrinsics
 2026-09-14 08:35:50 +03:00
Malcolm Jestadt bcb2d22311 BufferUtils: Optimize upload_untouched_skip_restart with AVX-512 paths 
- u16 path needs AVX-512-ICL because vpcompressw isn't included in skylake-x level AVX-512

- u32 path is untested as I couldn't find any games that hit it
 2026-09-10 19:17:26 +02:00
Malcolmandjpolo1224 6161ecd7aa PPU: Stop inverting float-to-int saturation on ARM64 
- This was breaking armored core 4/4a on ARM
- Original fix credit to jpolo1224 of armsx3 https://github.com/ARMSX2/ARMSX3/commit/87ccdb85152a707f5d0c8122ed39344b4648501e

Co-authored-by: jpolo1224 <[email protected]>
 2026-08-18 03:12:13 +02:00
Malcolm 03647fdb4e SPU LLVM: Break out of checksum hole scan 2026-07-01 13:30:05 +03:00
Malcolm 1b54e8910c SPU: Add some comments clarifying very obtuse code 2026-07-01 13:30:05 +03:00
Malcolm 3f27cb8ff5 SPU LLVM: Loop large checksum verification 2026-07-01 13:30:05 +03:00
Malcolm fa5b899411 SPU LLVM: Reduce dot comparison result with addv 2026-07-01 13:30:05 +03:00
Whatcookie 35f65c2244 SPU LLVM: Add ARM checksum UABA path 2026-07-01 13:30:05 +03:00
Malcolm ed145540a2 SPU: Use multiply-accumulate comparisons for cmp_rdata and verification 2026-07-01 13:30:05 +03:00
Whatcookie 18fe6eeb71 SPU LLVM: Use ARM USHL for masked infinite shifts 
- LLVM can't handle the select pattern we use to avoid poison values for large shifts
- So let's just use the intrinsic to avoid poison values altogether for now
- https://github.com/llvm/llvm-project/issues/200698
 2026-07-01 12:10:35 +03:00
Malcolm 87608865b6 SPU LLVM: Use SVE2 XAR for constant rotates 2026-06-24 09:04:24 +03:00
Malcolm e7165cbe99 RSX: Use one-shot cacheline wait in semaphore acquire 2026-06-07 15:55:28 +02:00
Malcolm d85f1c7155 RSX: Add hardware spin_wait helper, use it in flush requests 2026-06-07 15:55:28 +02:00
Whatcookie 2d1be09180 SPU LLVM: Use TBL for AArch64 ROTQBY shuffles 2026-06-06 18:51:35 +02:00
Malcolm 3164d44952 SPU LLVM: Use I8MM for GBH and GBB 2026-06-05 23:19:35 +02:00
Malcolm 6349ea2ee9 SPU LLVM: SVE multiply optimizations 
- Reduces most SPU multiply instructions to a single operation
- Add SVE length detection, only use SVE instructions for 128b sve for
  now
 2026-06-05 14:58:24 +02:00
Whatcookie 2f2ac69d60 SPU LLVM: Idiomatic FSM implementation 
- Compiles down to just 2 instructions on Neon, instead of falling back to scalar instructions
- Remove this workaround when LLVM fixes this issue upstream: https://github.com/llvm/llvm-project/issues/200325
 2026-06-05 09:48:16 +02:00
Malcolm 4a92d96cf4 SPU LLVM: Use 128-bit SVE2 for FMS 2026-06-05 08:41:17 +02:00
Malcolm c11979d124 Revert "SPU LLVM: Remove dead interpreter ret fallback" 
This reverts commit 3058a71d72.
 2026-05-29 02:24:05 +02:00
Malcolm 3058a71d72 SPU LLVM: Remove dead interpreter ret fallback 2026-05-28 14:10:51 +03:00
Malcolm a87d175295 SPU LLVM: Retry ARM64 TBL2 register scavenger failures 
- Some SPU programs inexplicably fail to compile when TBL2/TBX2 are used.
- As an insane workaround, first try to compile with TBL2/TBX2, if LLVM crashes while compiling, try to compile the same program without TBL2/TBX2.
 2026-05-27 02:46:11 +03:00
Malcolm dff29a7864 PPU/SPU LLVM: Use arm shuffles in recompilers instead of emulating x86 pshufb 
> - SHUFB from 9 instructions down to 5
> - Though it should be 4 if LLVM would just emit BCAX...
 2026-05-27 02:46:11 +03:00
Malcolm 7e436f9bf1 SPU LLVM: Optimize SPU multiplies for ARM 
- Saves 2 instructions in MPY, 1 instruction in MPYU, 2 instructions in MPYS, 2 instructions in MPYA, 1 instruction in MPYI, and 2 instructions in MPYUI
 2026-05-20 10:54:13 +03:00
Malcolm 61a2604824 SPU LLVM: Inline reading/writing the decrementer for ARM too 
- Try switching to llvm's readycyclecounter, which should map to rdtsc on x86 too.
 2026-05-17 02:26:42 +03:00
Malcolm 320e8d634a SPU LLVM: Workaround bad LLVM codegen for FCGT on AARCH64 
- LLVM was emitting a nasty sequence for select instead of just using BSL, so let's try using inline assembly.
 2026-05-13 15:20:39 +03:00
Malcolm 1627757608 SPU LLVM: Emulate GBB with udot/sdot 
Greatly simplifies GB, GBH, and GBH. Uses udot/sdot with power of two
masks to shift values and sum them in a single step, effectively
gathering them
 2026-03-15 08:48:18 +02:00
Malcolm 4542020c86 SPU LLVM: ARM64: Use UDOT for emulating SUMB 2026-03-15 08:48:18 +02:00
Malcolm b2469039af ARM64: Detect some arm features and let LLVM know if they are or aren't present via attributes 
- On x86, LLVM has robust detection for the CPU name. If a CPU like skylake has AVX disabled, it will fall back to something without AVX (nehalem)
- On ARM, detection is not as robust. For instance, on my snapdragon 8 gen 2, it assumes that we have SVE support, as the cortex-x3 supports SVE.
- If an ARM cpu is paired with other cpus from another generation which doesn't support the same instructions as the cortex-x3, or if the cortex-x3 just has SVE disabled for no apparant reason (in the case of the snapdragon 8 gen 2)
- We need to actually detect that ourselves.
- Beyond SVE also detect support for some instructions that might be useful SPU LLVM when optimized with intrinsics.
 2026-02-11 08:19:59 +02:00
Malcolm 93fd33a19a ARM: Use ISB instead of yield in place of x86 pause 
ISB isn't an exact match for pause, but it does slow down execution at least a litle.
Unfortunately, yield does nothing on machines without SMT (99% of aarch64 machines)
 2026-02-06 07:54:44 +02:00
Malcolm 0f85e9123e utils: Scale busy_wait according to arm timer frequency 
> - This is a fatal issue that was impacting arm builds, since busy_waits were written assuming an approx 3Ghz x86 machine
> and most arm machines have a hardware timer that runs south of 100mhz, meaning the top items in the profiler were calls to busy_wait();
> all over the code. Fixing this is a very significant speedup, on my snapdragon 8 gen 2 device. 27->37FPS in Metal Gear Rising, but almost
> all games benefit when run on ARM.
 2026-01-17 10:07:01 +02:00
Malcolm 760c35eec8 PPU LLVM: Use arm fmax/fmin for vmaxfp/vminfp 
- Arm fmax/fmin match altivec behaviour regarding nan behaviour
 2026-01-17 09:20:13 +02:00
Malcolm eaebd3426e LLVM: enable FMA for ARM cpus unconditionally 
- All armv8 machines should have FMA.
- Should be a speedup for snapdragon elite and apple machines.
 2026-01-15 08:29:33 +02:00
Malcolm Jestadt c52920755a SPU LLVM: Don't use vperm2b256to128 outside of CPUTranslator.h 
- The vperm2b function uses vperm2b256to128 when it's ideal
 2025-03-25 10:42:02 +02:00
Whatcookie d9071abd8b Utils: Remove AVX10-256 detection (#16904) 
- Intel recently removed 256b AVX10 from the AVX10 spec.
 2025-03-22 13:28:45 +02:00
Malcolm Jestadt f9a72e8d75 SPU LLVM: Preserve sign on inf to NaN conversion in spu_re_acc with vfixupimmps 2025-03-15 10:46:08 +02:00
Whatcookie bfb9dfea7e RSX: ProgramStateCache loops optimizations 2025-03-07 09:54:12 +02:00
Malcolm Jestadt 1920aee415 RSX: Fix issue where linux builds could hit illegal instruction on machines without AVX-512 
- Place avx-512 function attributes in their own functions
 2025-03-03 15:58:55 +03:00
Malcolm Jestadt 6bd1ab576c RSX: Use AVX-512-ICL code in get_vertecx_program_ucode_hash and in vertex_program_compare 
- Code is about 4 times as fast on my zen4 machine
- Should be twice as fast on zen5 machines with full width AVX-512
 2025-03-02 09:07:07 +02:00
Malcolm Jestadt bd49c6bedb SPU LLVM: Small FCGT optimization 2025-02-22 07:35:14 +02:00
Malcolm Jestadt 7b9aaacc4b RSX: ProgramStateCache logic cleanup and microoptimizations 
- Eliminate some redundant checks in fragment and vertex comparison functions
- Add is_any_src_constant optimization, eliminates 1 instruction per loop
 2025-02-16 12:28:10 +02:00
Malcolm Jestadt d891b83e4b RSX: Use checksum with rotated inputs for shader hashing instead of FNV 
- Raises FPS from ~180 to ~200 in Ninja Gaiden
 2025-02-16 12:28:10 +02:00
Malcolm Jestadt a9b0f76698 cmake: Enable LTO for rpcs3_emu target 
- Provides a small speedup and saves some space in the binary.
 2025-02-12 09:46:53 +02:00
Malcolm Jestadt dfd83bc7a4 SPU LLVM: Add two dependency chains for SPU verification 
- Should restore performance to match the xorsum builds
 2025-02-11 12:30:21 +02:00
Malcolm Jestadt 911f0928cf SPU LLVM: Replace xorsum with simple checksum 
- Fixes crashes in GTAV
 2025-02-01 21:40:30 +02:00
Malcolm Jestadt 506d92107c SPU LLVM: Use 512bit xorsum for SPU verification 
- Provides a 2-3% uplift in SPU limited titles
- Removes the full_width_avx512 option
- Adds a precise spu verification option, for debugging (config file only)
 2025-01-31 12:03:05 +02:00
WhatcookieandElad 385710672f SPU LLVM: Recognize ROTYQBYI and ROTQBI rotation pattern (#16409) 
Co-authored-by: Elad <[email protected]>
 2024-12-22 10:29:15 +02:00
Malcolm Jestadt 967adaf9db SPU LLVM: Compute frest exponent at runtime rather than using the lookup table 
- Provides a small speedup and smaller codesize
 2024-10-05 20:44:23 +03:00
Malcolm Jestadt 8ca60df1ab SPU LLVM: Add optimized path for spu_re_acc special cases 
- Uses vfixupimmps (AVX-512), 5 instructions down to 1
 2024-10-05 20:44:23 +03:00
Malcolm Jestadt d1bea790f3 SPU LLVM: Optimize GB/GBH/GBB with a GFNI path 
- Abuses GFNI to extract bits from bytes, from 5->2 instructions in most cases
 2023-10-01 23:05:28 +03:00
Malcolm Jestadt 05b6108c66 SPU LLVM: Optimize remaining rotate instructions which take a twos compliment value as input 
ROTQMBYBI looks for -7 for it's twos compliment construction
 2023-09-23 08:00:09 +03:00
Malcolm Jestadt 290ff5b839 Zero register optimization for AVX-512-VBMI 
- Take advantage of the fact that AVX instructions zero the upper 128 bits for a nice optimization when one input vector is zeroed
 2023-08-28 05:09:30 +03:00
Malcolm Jestadt f2e782f5dd SPU LLVM: Inline timer reads for WrDec and RdDec 
- Uses RDTSC to emulate the spu decrementer
 2023-08-13 00:16:35 +03:00
Malcolm Jestadt 512f0a814c SPU LLVM: Fix for AVX-512 CFLTU path 
- vcvvtps2udq doesn't turn negative numbers into 0, fix by using signed integer max with 0 instead of vrangeps
 2023-08-12 02:55:08 +03:00
Whatcookie d4cf12bc17 LV2: Improve sys_timer_usleep by using CPU usermode waiting 
* Linux: set timerslack to minimum value
- Linux delays the wakeup of threads to save power, this feature isn't needed for this application

* Utils: Add detection for waitpkg and monitorx extensions
- These instructions are used for user mode wait instructions

* lv2: Use user mode wait instructions instead of yielding when appropriate
 2023-08-05 11:49:30 +03:00
Whatcookie fd6829f757 SPU LLVM: AVX-512 optimization for CFLTU (#14384) 
- Takes advantage of vrangeps and the new float to uint instructions from AVX-512
- Down from 6 to 3 instructions

TODO: Somehow ensure that this is what llvm outputs using CreateFPToUI?
 2023-07-29 09:01:01 +03:00
Whatcookie 4ecb06c901 SPU LLVM: Optimize common SFI+ROTQMBY pattern 2023-07-28 10:26:40 +03:00
Whatcookie 375bc4cc69 Utils: Add initial AVX10 support 
- Adds detection for AVX10 features
- Also adds new bools for 256-wide AVX-512 instructions, indicated by either AVX-512 support, or AVX10
 2023-07-28 06:55:20 +03:00
Malcolm Jestadt ee7475a9d4 SPU LLVM: Handle SHUFB special cases with a lookup table 
- Needs 3 instructions to handle the special cases, since x86 lacks an 8 bit simd shift instruction
 2023-07-18 22:27:45 +03:00
Malcolm Jestadt 813f7b50c1 SPU LLVM: Minor SUMB AVX-512 path optimization 
- Tweak shuffle to allow LLVM to emit a cheap blend instruction instead of the expensive VPERMI2W instruction
 2023-01-27 13:06:48 +03:00
Malcolm Jestadt d8897c585d PPU/SPU LLVM: Allow Zen4 cpus to use VPERMI2B/VPERMT2B instead of the vperm2b256to128 path 
- Zen4 based cpus can process VPERM2B in a single uop, unlike intel where it is 3 uops.
 2022-10-01 15:38:29 +03:00
Malcolm Jestadt 51e6d0a336 SPU LLVM: Add integer compare optimization for FCMGT 2022-07-29 11:59:59 +03:00
Malcolm Jestadt 0d022d420b RSX: Add more wide paths for upload_untouched 
- Adds AVX512 path for upload_untouched u16 with primitive restart, and
  AVX2 and AVX512 paths for upload_untouched without restart
- The AVX512 paths handle the remainder in simd code with masking, which
  provided a large speedup
- On my i5-1135G7 in demons souls benchmarking a scene in boletaria with
  a lot of geometry on screen via perf:
SSE4_1                      0.64%
AVX2                        0.59%
AVX512                      0.56%
AVX512 w/ remainder masking 0.51%
 2022-06-12 06:23:55 +03:00
Malcolm Jestadt ebeeafc94f SPU LLVM: Use vrangeps in clamp_smax 
- This instruction can clamp a value between a range of values, something which previously needed 2 instructions.
- With the immediate byte set to 0x2 it will compute the minimum between the absolute value of the first input and the second input, and then copy the sign from the first input to the result.
 2022-06-11 18:25:31 +03:00
Malcolm Jestadt 64616f1408 SPU LLVM: Microfixes 
- Avoid vpermb path in shufb when op.ra == op.rb
- Reverse indices with (c ^ 0xf) rather than (~c) in vpermb path, vpternlogd is a 3 input operation and requires needless mov instructions to avoid destroying inputs
 2022-06-08 22:50:30 +03:00
Malcolm Jestadt 1227b0a633 SPU LLVM: Reneable icelake shufb paths 
- The previous code works just fine
 2022-06-05 13:08:00 +03:00
Malcolm Jestadt 0e5514003a SPU LLVM: Optimize LQR/STQR 
- Avoid type mismatch between adds that prevented llvm from combining the operations
 2022-06-03 16:16:28 +03:00
Malcolm Jestadt e9dfb3cb63 SPU LLVM: Fixup for inline MFC transfers 
- Could previsouly segfault when src and dst were swapped. Just use unaligned instructions instead.
 2022-05-29 19:08:36 +03:00
Malcolm Jestadt 6f4398889e SPU LLVM: Optimize inline MFC transfers 
- Use wider instructions when possible
 2022-05-29 15:32:25 +03:00
Malcolm Jestadt 5ad4b6249e Update LLVM commit 
- Contains a commit that makes AVX-512 code size smaller
 2022-05-27 18:40:57 +03:00
Malcolm Jestadt 91673f8fdc SPU LLVM: Add relaxed xfloat option 
- This new setting is on by default
- It's active when approximate default is disabled
- Approximate xfloat is now exposed to the gui
 2022-01-31 08:02:48 +03:00
Malcolm Jestadt 31a5a77ae5 SPU: Use REP MOVSB in do_dma_transfer 
- Try to use REP MOVSB when the size of the transfer is above a certain threshold
- This threshold is determined by the ERMS and FSRM cpuid flags
- The threshold values are (roughly) taken from GLIBC
- A threshold of 0xFFFFFFFF indicates that the cpu has neither flag
 2022-01-02 21:35:46 +03:00
Malcolm Jestadt 2f93df480b SPU LLVM: Disable affineqb shufb paths temporarilly 2021-12-10 19:32:10 +03:00
Malcolm Jestadt 0617e9e14b SPU LLVM: Fix vgf2p8affineqb usage 
- Reverse the order of the bytes in the selection masks. Previously it was assumed that byte 0 would determine the output of bit 0, but byte 7 determines the output of bit 0.
 2021-12-06 12:34:11 +03:00
Malcolm Jestadt 3fde455932 SPU LLVM: Optimize branch following ORX 
- test the input of ORX directly for zeroes, instead of the result
 2021-11-11 12:58:38 +03:00
Malcolm Jestadt 7573d7289b SPU LLVM: Hook up 128 bit spu verification 
- Also fix FMA enablement for sapphirerapids
 2021-11-06 21:12:12 +03:00
Whatcookie bf6044fced SPU/SYSINFO: Disable TSX by default for TSX-FA cpus (#11105) 
- Also detect the new RTM_ALWAYS_ABORT bit in cpuid
- This new bit indicates that RTM is disabled in the microcode
- On cpus with RTM_ALWAYS_ABORT TSX can be renabled by writing 0x4 to the msr 0x0000010F
 2021-11-04 16:44:25 +00:00
Malcolm Jestadt 37383f4217 SPU ASMJIT: Disable 512 wide spu verification 
- Apparantly this crashes every game.
 2021-11-01 20:04:26 +03:00
Malcolm Jestadt f06c8b22e8 PPU/SPU LLVM: Emulate VPERM2B with a 256 bit wide VPERMB 
- Save 1 uop by using 256 wide VPERMB instead of VPERM2B. (Compiles down to a vinserti128 and vpermb)
 2021-10-13 17:51:54 +03:00
Malcolm Jestadt 2cfa5406e7 LLVM DSL: reimplement vdbpsadbw 2021-09-30 13:22:35 +03:00
Malcolm Jestadt 86716dc37b SPU LLVM: Optimize branches following byteswaps 
- The first element can be extracted via vmovd rather than vpextrd, which saves 1 uop.
 2021-09-30 13:22:35 +03:00
Malcolm Jestadt f9ab077908 SPU LLVM: Use VDBPSADBW in SUMB 
- This instruction can be used to sum bytes horrizontally if the second input vector is all zeroes.
 2021-09-30 13:22:35 +03:00
Malcolm Jestadt 43cc62d267 SPU LLVM: Add m_use_vnni 
- Alderlake and Sapphirerapids will require an update to the llvm fork before they can be detected
 2021-08-31 14:02:05 +03:00
Malcolm Jestadt d304b52391 SPU LLVM: Add VNNI optimized variant of sumb 
- Uses vpdpbusd to horrizontally add values, for some reason this is much faster than the normal horizontal add instructions.
 2021-08-31 14:02:05 +03:00
Malcolm Jestadt a86b278115 SPU LLVM: Expand byteswap elimination to more instructions 2021-08-31 14:02:05 +03:00
Whatcookie d0451932bf Offset get_timebased_time at game boot (#10744) 
- Avoids game bugs in the case where games convert the value read from the clock to a float before performing delta time calculations
 2021-08-23 13:06:02 +01:00
Whatcookie c62deeefd4 SPU LLVM: Add approximate FCEQ/FCMEQ (#8729) 
- It's 100% accurate, but will sit under approx xfloat anyways
- Attempts to use a single instruction when 1 value is constant
 2021-08-22 10:13:34 +03:00
Malcolm Jestadt 7c2b08b9b6 SPU LLVM: Expand branch optimizations for more instructions 2021-05-29 13:07:35 +03:00
Malcolm Jestadt 52780e65e7 SPU LLVM: Optimize branching 
- Detect a pattern where vpmovmskb and a check against the sign bit can be used instead of checking against zero
 2021-05-17 16:59:20 +03:00
Malcolm Jestadt 6247969ede SPU LLVM: Absolute final fixes for icelake shufb paths 
- The constant mask was accessing bits in reverse order of what was expected
 2021-04-21 11:00:02 +03:00
Malcolm Jestadt efd38fa940 SPU LLVM: Improve byteswap elimination 
- Use the data before it has been swapped rather than relying on a second byteswap to cancel out the first
 2021-04-20 23:24:21 +03:00
Malcolm Jestadt 551472220e SPU LLVM: Remove icelake shufb paths for now 2021-04-20 23:24:21 +03:00
Malcolm Jestadt 53f13a9721 SPU LLVM: Final fixup for icelake shufb paths 
- The cause of the problems was due to the constant mask for gf2p9affineqb being used as the first argument, instead of the second argument.
 2021-04-20 13:07:24 +03:00