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small fixup which enables the issuing of the aforementioned instruction (w/o operands), on MS/Intel syntax.

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Differential Revision: https://reviews.llvm.org/D26913



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Coby Tayree
2016-11-21 15:50:56 +00:00
parent f570b5fd16
commit bbc769fbf0
2 changed files with 3 additions and 1 deletions
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2
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@@ -2536,7 +2536,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
(Name == "smov" || Name == "smovb" || Name == "smovw" ||
Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
(Operands.size() == 1 || Operands.size() == 3)) {
if (Name == "movsd" && Operands.size() == 1)
if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
DefaultMemDIOperand(NameLoc));

2
test/MC/X86/intel-syntax.s
View File

@@ -77,6 +77,8 @@ _main:
vpgatherdd XMM10, XMMWORD PTR [R15 + 2*XMM9], XMM8
// CHECK: movsd -8, %xmm5
movsd XMM5, QWORD PTR [-8]
// CHECK: movsl (%rsi), %es:(%rdi)
movsd
// CHECK: movl %ecx, (%eax)
mov [eax], ecx
// CHECK: movl %ecx, (,%ebx,4)