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CET opcode change / operand change for SETSSBSY
Change-Id: I866a5c25a670050b6c8f36609ff66d6b8b1bcfda (cherry picked from commit 59dca5d3cdf20a773c96678a3d29dda6fa3b7a49)
This commit is contained in:
Mark Charney
committed by
Mark Charney
Mark Charney
parent
c31ccf70bd
commit
58f47a58ba
@@ -1,19 +1,25 @@
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#BEGIN_LEGAL
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#INTEL CONFIDENTIAL
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#
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#Copyright (c) 2017 Intel Corporation
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#Copyright (c) 2017, Intel Corporation. All rights reserved.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#The source code contained or described herein and all documents
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#related to the source code ("Material") are owned by Intel Corporation
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#or its suppliers or licensors. Title to the Material remains with
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#Intel Corporation or its suppliers and licensors. The Material
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#contains trade secrets and proprietary and confidential information of
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#Intel or its suppliers and licensors. The Material is protected by
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#worldwide copyright and trade secret laws and treaty provisions. No
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#part of the Material may be used, copied, reproduced, modified,
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#published, uploaded, posted, transmitted, distributed, or disclosed in
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#any way without Intel's prior express written permission.
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#
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#No license under any patent, copyright, trade secret or other
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#intellectual property right is granted to or conferred upon you by
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#disclosure or delivery of the Materials, either expressly, by
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#implication, inducement, estoppel or otherwise. Any license under such
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#intellectual property rights must be express and approved by Intel in
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#writing.
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#END_LEGAL
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#
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#
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@@ -33,7 +39,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()
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PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()
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OPERANDS: MEM0:w:q:u64
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IFORM: CLRSSBSY_MEMu64
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}
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@@ -47,7 +53,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1
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OPERANDS:
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IFORM: ENDBR32
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}
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@@ -61,7 +67,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1
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OPERANDS:
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IFORM: ENDBR64
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}
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@@ -75,7 +81,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W0
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W0
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OPERANDS:
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IFORM: INCSSPD
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}
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@@ -89,7 +95,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W1 mode64
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f3_refining_prefix W1 mode64
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OPERANDS:
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IFORM: INCSSPQ
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}
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@@ -103,7 +109,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1
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OPERANDS: REG0=GPR32_B():w:d:u32
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IFORM: RDSSPD_GPR32u32
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}
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@@ -117,7 +123,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1
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PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1
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OPERANDS: REG0=GPR64_B():w:q:u64
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IFORM: RDSSPQ_GPR64u64
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}
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@@ -131,7 +137,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix
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PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix
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OPERANDS: MEM0:rw:q:u64
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IFORM: RSTORSSP_MEMu64
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}
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@@ -145,7 +151,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix
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OPERANDS:
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IFORM: SAVESSP
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}
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@@ -159,9 +165,9 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] f3_refining_prefix MODRM()
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OPERANDS: MEM0:w:q:u64
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IFORM: SETSSBSY_MEMu64
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PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix
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OPERANDS:
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IFORM: SETSSBSY
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}
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@@ -173,7 +179,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0
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PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0
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OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
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IFORM: WRSSD_MEMu32_GPR32u32
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}
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@@ -187,7 +193,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64
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PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64
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OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
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IFORM: WRSSQ_MEMu64_GPR64u64
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}
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@@ -201,7 +207,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0
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PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0
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OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
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IFORM: WRUSSD_MEMu32_GPR32u32
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}
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@@ -215,7 +221,7 @@ CATEGORY: CET
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EXTENSION: CET
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ISA_SET: CET
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REAL_OPCODE: Y
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PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64
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PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64
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OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
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IFORM: WRUSSQ_MEMu64_GPR64u64
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}
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