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split CMOV and FCMOV in to their own isa sets

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Change-Id: I9b24e198fe0b9fe1611b7b08e87981b6842f7436
(cherry picked from commit 86238265a5bb649ef13cdc22b66458907936520c)
This commit is contained in:
Mark Charney
2017-06-22 13:49:42 -04:00
parent 09843ea903
commit b6beda320c
2 changed files with 34 additions and 34 deletions
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4
datafiles/xed-chips.txt
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@@ -59,12 +59,12 @@ ALLREAL: ALL_OF(PENTIUMMMXREAL)
# P6, PentiumPro, PPRO:
# The SSE_PREFETCH were on P6 as fat NOPs, but XED only recognizes them on >=PENTIUM3
PENTIUMPRO: ALL_OF(PENTIUM) PPRO RDPMC FAT_NOP PREFETCH_NOP # NO MMX (Orig P6)
PENTIUMPRO: ALL_OF(PENTIUM) PPRO CMOV FCMOV RDPMC FAT_NOP PREFETCH_NOP # NO MMX (Orig P6)
# FCMOV*, CMOV*, RDPMC, SYSCALL, SYSENTER, SYSEXIT,SYSRET, UD2, F[U]COMI[P]
# note conflict with PENTIUM2 addition of SYSENTER/SYSEXIT
PENTIUM2: ALL_OF(PENTIUM) PENTIUMMMX PPRO FAT_NOP RDPMC PREFETCH_NOP FXSAVE
PENTIUM2: ALL_OF(PENTIUM) PENTIUMMMX PPRO CMOV FCMOV FAT_NOP RDPMC PREFETCH_NOP FXSAVE
# FXSAVE/FXRSTOR, SYSENTER,SYSEXIT P6
# we keep SSEMXCSR separate from SSE to accommodate chip-check for KNC

64
datafiles/xed-isa.txt
View File

@@ -726,7 +726,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -737,7 +737,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -748,7 +748,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -759,7 +759,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -830,7 +830,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -841,7 +841,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -852,7 +852,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -863,7 +863,7 @@ ATTRIBUTES: NOTSX
CPL : 3
CATEGORY : FCMOV
EXTENSION : X87
ISA_SET : PPRO
ISA_SET : FCMOV
FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ]
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
@@ -8768,7 +8768,7 @@ ICLASS : CMOVO
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ of-tst ]
PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8780,7 +8780,7 @@ ICLASS : CMOVNO
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ of-tst ]
PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8792,7 +8792,7 @@ ICLASS : CMOVB
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ cf-tst ]
PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8804,7 +8804,7 @@ ICLASS : CMOVNB
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ cf-tst ]
PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8816,7 +8816,7 @@ ICLASS : CMOVZ
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ zf-tst ]
PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8828,7 +8828,7 @@ ICLASS : CMOVNZ
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ zf-tst ]
PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8840,7 +8840,7 @@ ICLASS : CMOVBE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ cf-tst zf-tst ]
PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -8852,7 +8852,7 @@ ICLASS : CMOVNBE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ cf-tst zf-tst ]
PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11222,7 +11222,7 @@ ICLASS : CMOVS
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst ]
PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11232,7 +11232,7 @@ ICLASS : CMOVS
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst ]
PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11242,7 +11242,7 @@ ICLASS : CMOVNS
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst ]
PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11252,7 +11252,7 @@ ICLASS : CMOVNS
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst ]
PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11262,7 +11262,7 @@ ICLASS : CMOVP
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ pf-tst ]
PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11272,7 +11272,7 @@ ICLASS : CMOVP
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ pf-tst ]
PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11282,7 +11282,7 @@ ICLASS : CMOVNP
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ pf-tst ]
PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11292,7 +11292,7 @@ ICLASS : CMOVNP
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ pf-tst ]
PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11302,7 +11302,7 @@ ICLASS : CMOVL
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst ]
PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11312,7 +11312,7 @@ ICLASS : CMOVL
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst ]
PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11322,7 +11322,7 @@ ICLASS : CMOVNL
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst ]
PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11332,7 +11332,7 @@ ICLASS : CMOVNL
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst ]
PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11342,7 +11342,7 @@ ICLASS : CMOVLE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11352,7 +11352,7 @@ ICLASS : CMOVLE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
@@ -11362,7 +11362,7 @@ ICLASS : CMOVNLE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
@@ -11372,7 +11372,7 @@ ICLASS : CMOVNLE
CPL : 3
CATEGORY : CMOV
EXTENSION : BASE
ISA_SET : PPRO
ISA_SET : CMOV
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r