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cleanup of RIP handling on branches

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* rIP() was effective address size (EASZ) sensitive and that was
    wrong.

  * some branch instructions have 64b mode only patterns.  They now
    use XED_REG_RIP.

  * some branch instructions have not64 mode only patterns.  They now
    use XED_REG_EIP.

  * some branch patterns use common patterns. They use rIP() but now
    rIP() is mode-only sensitive. In 64b mode, RIP gets updated.  And
    in non64 modes, EIP gets updated. When EOSZ is 16b, the full 32b
    EIP is updated, under a mask.

  * Still to do: need to rebase the existing tests and add new ones.
    More testing required.

Change-Id: Id6124cab3ec58db702c359b7621e3a17a9d39dfa
This commit is contained in:
Mark Charney
2017-06-23 22:48:41 -04:00
parent 27e3ad03f1
commit dc0e662d38
2 changed files with 82 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

153
datafiles/xed-isa.txt
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@@ -3802,9 +3802,9 @@ ISA_SET : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0xE8 not64 BRDISPz()
OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP
PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64()
OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM()
OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
@@ -6490,9 +6490,9 @@ ISA_SET : I86
FLAGS : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNO
@@ -6503,9 +6503,9 @@ ISA_SET : I86
FLAGS : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JB
@@ -6516,9 +6516,9 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNB
@@ -6529,9 +6529,9 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JZ
@@ -6542,9 +6542,9 @@ ISA_SET : I86
FLAGS : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNZ
@@ -6555,9 +6555,9 @@ ISA_SET : I86
FLAGS : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JBE
@@ -6568,9 +6568,9 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNBE
@@ -6581,9 +6581,9 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JS
@@ -6594,9 +6594,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNS
@@ -6607,9 +6607,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JP
@@ -6620,9 +6620,9 @@ ISA_SET : I86
FLAGS : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNP
@@ -6633,9 +6633,9 @@ ISA_SET : I86
FLAGS : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JL
@@ -6646,9 +6646,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNL
@@ -6659,9 +6659,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JLE
@@ -6672,9 +6672,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNLE
@@ -6685,9 +6685,9 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : TEST
@@ -7018,11 +7018,14 @@ CATEGORY : CALL
ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET : I86
COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP
PATTERN : 0x9A not64 BRDISPz() UIMM16()
OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP
OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP
}
{
ICLASS : FWAIT
@@ -7980,7 +7983,7 @@ EXTENSION : BASE
ISA_SET : I86
FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ]
PATTERN : 0xCE not64
OPERANDS : REG0=rIP():w:SUPP
OPERANDS : REG0=XED_REG_EIP:w:SUPP
}
{
ICLASS : IRET
@@ -8013,7 +8016,7 @@ EXTENSION : LONGMODE
FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
PATTERN : 0xCF EOSZ=3 mode64
# FIXME: This is only an approximate width for the stack pops
OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP
OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=XED_REG_RIP:w:SUPP
}
{
ICLASS : AAM
@@ -8195,9 +8198,9 @@ EXTENSION : BASE
ISA_SET : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0xE9 not64 BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
PATTERN : 0xE9 mode64 FORCE64() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
{
ICLASS : JMP_FAR
@@ -8209,7 +8212,7 @@ ATTRIBUTES : FAR_XFER NOTSX
EXTENSION : BASE
ISA_SET : I86
PATTERN : 0xEA not64 BRDISPz() UIMM16()
OPERANDS : PTR:r:p IMM0:r:w REG0=rIP():w:SUPP
OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP
}
{
ICLASS : JMP
@@ -8217,8 +8220,10 @@ CPL : 3
CATEGORY : UNCOND_BR
EXTENSION : BASE
ISA_SET : I86
PATTERN : 0xEB DF64() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP
PATTERN : 0xEB not64 BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
PATTERN : 0xEB mode64 FORCE64() BRDISP8()
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
}
{
ICLASS : IN
@@ -8394,7 +8399,7 @@ EXTENSION : LONGMODE
ISA_SET : LONGMODE
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
PATTERN : 0x0F 0x05 mode64 FORCE64()
OPERANDS : REG0=rIP():w:SUPP
OPERANDS : REG0=XED_REG_RIP:w:SUPP
COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD
}
{
@@ -9456,7 +9461,7 @@ FLAGS : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
{
ICLASS : JO
@@ -9480,7 +9485,7 @@ ISA_SET : I86
FLAGS : READONLY [ of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNO
@@ -9492,7 +9497,7 @@ FLAGS : READONLY [ of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9505,7 +9510,7 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JB
@@ -9517,7 +9522,7 @@ FLAGS : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9531,7 +9536,7 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
@@ -9544,7 +9549,7 @@ FLAGS : READONLY [ cf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9557,7 +9562,7 @@ ISA_SET : I86
FLAGS : READONLY [ zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JZ
@@ -9569,7 +9574,7 @@ FLAGS : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9582,7 +9587,7 @@ ISA_SET : I86
FLAGS : READONLY [ zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
@@ -9595,7 +9600,7 @@ FLAGS : READONLY [ zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9609,7 +9614,7 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JBE
@@ -9621,7 +9626,7 @@ FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -9635,7 +9640,7 @@ ISA_SET : I86
FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNBE
@@ -9647,7 +9652,7 @@ FLAGS : READONLY [ cf-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12158,7 +12163,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JS
@@ -12170,7 +12175,7 @@ FLAGS : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12183,7 +12188,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNS
@@ -12195,7 +12200,7 @@ FLAGS : READONLY [ sf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12209,7 +12214,7 @@ ISA_SET : I86
FLAGS : READONLY [ pf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JP
@@ -12221,7 +12226,7 @@ FLAGS : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12234,7 +12239,7 @@ ISA_SET : I86
FLAGS : READONLY [ pf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNP
@@ -12246,7 +12251,7 @@ FLAGS : READONLY [ pf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12259,7 +12264,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JL
@@ -12271,7 +12276,7 @@ FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12285,7 +12290,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNL
@@ -12297,7 +12302,7 @@ FLAGS : READONLY [ sf-tst of-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12311,7 +12316,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JLE
@@ -12323,7 +12328,7 @@ FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}
@@ -12337,7 +12342,7 @@ ISA_SET : I86
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
}
{
ICLASS : JNLE
@@ -12349,7 +12354,7 @@ FLAGS : READONLY [ sf-tst of-tst zf-tst ]
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32()
OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}

7
datafiles/xed-reg-tables.txt
View File

@@ -108,10 +108,9 @@ EASZ=2 | OUTREG=XED_REG_R15D
EASZ=3 | OUTREG=XED_REG_R15
xed_reg_enum_t rIP()::
EASZ=1 | OUTREG=XED_REG_IP
EASZ=2 | OUTREG=XED_REG_EIP
EASZ=3 | OUTREG=XED_REG_RIP
mode16 | OUTREG=XED_REG_EIP
mode32 | OUTREG=XED_REG_EIP
mode64 | OUTREG=XED_REG_RIP
#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 32b