2010-04-21 18:02:42 +00:00
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//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This register allocator allocates registers to a basic block at a time,
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// attempting to keep values in registers and reusing registers as appropriate.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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2011-06-02 18:35:30 +00:00
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#include "RegisterClassInfo.h"
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2010-04-21 18:02:42 +00:00
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#include "llvm/BasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2010-08-04 18:42:02 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2010-04-21 18:02:42 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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2010-05-14 21:55:50 +00:00
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STATISTIC(NumCopies, "Number of copies coalesced");
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2010-04-21 18:02:42 +00:00
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static RegisterRegAlloc
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fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
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namespace {
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class RAFast : public MachineFunctionPass {
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public:
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static char ID;
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2010-08-06 18:33:48 +00:00
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RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
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2010-10-19 17:21:58 +00:00
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isBulkSpilling(false) {
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initializePHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
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}
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2010-04-21 18:02:42 +00:00
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private:
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const TargetMachine *TM;
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MachineFunction *MF;
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2010-05-13 00:19:43 +00:00
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MachineRegisterInfo *MRI;
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2010-04-21 18:02:42 +00:00
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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2011-06-02 18:35:30 +00:00
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RegisterClassInfo RegClassInfo;
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2010-04-21 18:02:42 +00:00
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2010-05-17 02:07:22 +00:00
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// Basic block currently being allocated.
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MachineBasicBlock *MBB;
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2010-04-21 18:02:42 +00:00
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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// values are spilled.
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IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
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2010-05-11 23:24:45 +00:00
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// Everything we know about a live virtual register.
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struct LiveReg {
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2010-05-11 23:24:47 +00:00
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MachineInstr *LastUse; // Last instr to use reg.
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unsigned PhysReg; // Currently held here.
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unsigned short LastOpNum; // OpNum on LastUse.
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bool Dirty; // Register needs spill.
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2010-05-11 23:24:45 +00:00
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2010-05-11 23:24:47 +00:00
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LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
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2010-05-17 02:07:29 +00:00
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Dirty(false) {}
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2010-05-11 23:24:45 +00:00
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};
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typedef DenseMap<unsigned, LiveReg> LiveRegMap;
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2010-05-17 02:07:29 +00:00
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typedef LiveRegMap::value_type LiveRegEntry;
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2010-05-11 23:24:45 +00:00
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// LiveVirtRegs - This map contains entries for each virtual register
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2010-04-21 18:02:42 +00:00
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// that is currently available in a physical register.
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2010-05-11 23:24:45 +00:00
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LiveRegMap LiveVirtRegs;
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2010-04-21 18:02:42 +00:00
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2011-06-21 22:36:03 +00:00
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DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
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2010-08-04 18:42:02 +00:00
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2010-05-11 18:54:45 +00:00
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// RegState - Track the state of a physical register.
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enum RegState {
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// A disabled register is not available for allocation, but an alias may
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// be in use. A register can only be moved out of the disabled state if
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// all aliases are disabled.
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regDisabled,
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// A free register is not currently in use and can be allocated
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// immediately without checking aliases.
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regFree,
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2011-04-22 01:40:20 +00:00
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// A reserved register has been assigned explicitly (e.g., setting up a
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2010-05-11 18:54:45 +00:00
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// call parameter), and it remains reserved until it is used.
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regReserved
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2010-04-21 18:02:42 +00:00
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2010-05-11 18:54:45 +00:00
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// A register state may also be a virtual register number, indication that
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// the physical register is currently allocated to a virtual register. In
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2010-05-11 23:24:45 +00:00
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// that case, LiveVirtRegs contains the inverse mapping.
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2010-05-11 18:54:45 +00:00
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};
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// PhysRegState - One of the RegState enums, or a virtreg.
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std::vector<unsigned> PhysRegState;
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2010-04-21 18:02:42 +00:00
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// UsedInInstr - BitVector of physregs that are used in the current
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// instruction, and so cannot be allocated.
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BitVector UsedInInstr;
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2010-09-01 19:16:29 +00:00
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// SkippedInstrs - Descriptors of instructions whose clobber list was
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// ignored because all registers were spilled. It is still necessary to
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// mark all the clobbered registers as used by the function.
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2011-06-28 19:10:37 +00:00
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SmallPtrSet<const MCInstrDesc*, 4> SkippedInstrs;
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2010-06-04 18:08:29 +00:00
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2010-05-17 02:07:32 +00:00
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// isBulkSpilling - This flag is set when LiveRegMap will be cleared
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// completely after spilling all live registers. LiveRegMap entries should
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// not be erased.
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bool isBulkSpilling;
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2010-05-14 00:02:20 +00:00
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2010-05-17 15:30:32 +00:00
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enum {
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spillClean = 1,
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spillDirty = 100,
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spillImpossible = ~0u
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};
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2010-04-21 18:02:42 +00:00
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public:
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virtual const char *getPassName() const {
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return "Fast Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool runOnMachineFunction(MachineFunction &Fn);
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2010-05-17 02:07:22 +00:00
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void AllocateBasicBlock();
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2010-06-28 18:34:34 +00:00
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void handleThroughOperands(MachineInstr *MI,
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SmallVectorImpl<unsigned> &VirtDead);
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2010-04-21 18:02:42 +00:00
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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2010-05-15 06:09:08 +00:00
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bool isLastUseOfLocalReg(MachineOperand&);
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2010-05-17 02:07:29 +00:00
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void addKillFlag(const LiveReg&);
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2010-05-17 02:49:15 +00:00
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void killVirtReg(LiveRegMap::iterator);
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2010-05-12 18:46:03 +00:00
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void killVirtReg(unsigned VirtReg);
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2010-05-17 02:49:15 +00:00
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void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
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2010-05-17 02:07:32 +00:00
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
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2010-05-14 18:03:25 +00:00
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void usePhysReg(MachineOperand&);
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2010-05-17 02:07:22 +00:00
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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2010-05-17 15:30:32 +00:00
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unsigned calcSpillCost(unsigned PhysReg) const;
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2010-05-17 02:07:29 +00:00
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void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
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void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
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2010-05-17 03:26:09 +00:00
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LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint);
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LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint);
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2010-05-17 02:07:22 +00:00
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void spillAll(MachineInstr *MI);
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2010-05-18 21:10:50 +00:00
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bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
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2010-04-21 18:02:42 +00:00
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};
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char RAFast::ID = 0;
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}
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/// getStackSpaceFor - This allocates space for the specified virtual register
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/// to be held on the stack.
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int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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// Find the location Reg would belong...
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int SS = StackSlotForVirtReg[VirtReg];
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if (SS != -1)
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return SS; // Already has space allocated?
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// Allocate a new stack object for this spill location...
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int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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// Assign the slot.
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StackSlotForVirtReg[VirtReg] = FrameIdx;
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return FrameIdx;
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}
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2010-05-15 06:09:08 +00:00
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/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
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/// its virtual register, and it is guaranteed to be a block-local register.
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///
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bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
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// Check for non-debug uses or defs following MO.
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// This is the most likely way to fail - fast path it.
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2010-05-17 02:49:15 +00:00
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MachineOperand *Next = &MO;
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while ((Next = Next->getNextOperandForReg()))
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if (!Next->isDebug())
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2010-05-15 06:09:08 +00:00
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return false;
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// If the register has ever been spilled or reloaded, we conservatively assume
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// it is a global register used in multiple blocks.
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if (StackSlotForVirtReg[MO.getReg()] != -1)
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return false;
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// Check that the use/def chain has exactly one operand - MO.
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return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
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}
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2010-05-12 18:46:03 +00:00
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/// addKillFlag - Set kill flags on last use of a virtual register.
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2010-05-17 02:07:29 +00:00
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void RAFast::addKillFlag(const LiveReg &LR) {
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if (!LR.LastUse) return;
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MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
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2010-05-19 21:36:05 +00:00
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if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
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if (MO.getReg() == LR.PhysReg)
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2010-05-18 21:10:50 +00:00
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MO.setIsKill();
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else
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LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
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}
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2010-05-12 18:46:03 +00:00
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}
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/// killVirtReg - Mark virtreg as no longer available.
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2010-05-17 02:49:15 +00:00
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void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
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addKillFlag(LRI->second);
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const LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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2010-05-12 18:46:03 +00:00
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PhysRegState[LR.PhysReg] = regFree;
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2010-05-17 02:07:32 +00:00
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// Erase from LiveVirtRegs unless we're spilling in bulk.
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if (!isBulkSpilling)
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2010-05-17 02:49:15 +00:00
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LiveVirtRegs.erase(LRI);
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2010-05-11 23:24:45 +00:00
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}
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2010-05-11 18:54:45 +00:00
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/// killVirtReg - Mark virtreg as no longer available.
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void RAFast::killVirtReg(unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"killVirtReg needs a virtual register");
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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if (LRI != LiveVirtRegs.end())
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killVirtReg(LRI);
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2010-04-21 18:02:42 +00:00
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}
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2010-05-11 18:54:45 +00:00
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/// spillVirtReg - This method spills the value specified by VirtReg into the
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2010-08-21 20:19:51 +00:00
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/// corresponding stack slot if needed.
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2010-05-17 02:07:32 +00:00
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
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2010-05-11 18:54:45 +00:00
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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spillVirtReg(MI, LRI);
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2010-05-14 00:02:20 +00:00
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}
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/// spillVirtReg - Do the actual work of spilling.
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2010-05-17 02:07:22 +00:00
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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2010-05-17 02:49:15 +00:00
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LiveRegMap::iterator LRI) {
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LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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2010-05-11 23:24:45 +00:00
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2010-05-11 23:24:47 +00:00
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if (LR.Dirty) {
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2010-05-17 02:07:32 +00:00
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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2010-05-17 02:49:15 +00:00
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bool SpillKill = LR.LastUse != MI;
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2010-05-11 23:24:47 +00:00
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LR.Dirty = false;
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2011-01-09 03:05:53 +00:00
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DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI)
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<< " in " << PrintReg(LR.PhysReg, TRI));
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2010-05-17 02:49:15 +00:00
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const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
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int FI = getStackSpaceFor(LRI->first, RC);
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2010-05-17 02:07:22 +00:00
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DEBUG(dbgs() << " to stack slot #" << FI << "\n");
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2010-05-17 02:49:15 +00:00
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TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
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2010-04-21 18:02:42 +00:00
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++NumStores; // Update statistics
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2010-09-01 19:16:29 +00:00
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// If this register is used by DBG_VALUE then insert new DBG_VALUE to
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2010-08-04 18:42:02 +00:00
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// identify spilled location as the place to find corresponding variable's
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// value.
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2011-06-21 22:36:03 +00:00
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SmallVector<MachineInstr *, 4> &LRIDbgValues = LiveDbgValueMap[LRI->first];
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for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
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MachineInstr *DBG = LRIDbgValues[li];
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2010-09-01 19:16:29 +00:00
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const MDNode *MDPtr =
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2010-08-04 18:42:02 +00:00
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DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
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int64_t Offset = 0;
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if (DBG->getOperand(1).isImm())
|
|
|
|
Offset = DBG->getOperand(1).getImm();
|
2010-08-06 00:26:18 +00:00
|
|
|
DebugLoc DL;
|
|
|
|
if (MI == MBB->end()) {
|
|
|
|
// If MI is at basic block end then use last instruction's location.
|
|
|
|
MachineBasicBlock::iterator EI = MI;
|
|
|
|
DL = (--EI)->getDebugLoc();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
DL = MI->getDebugLoc();
|
2010-09-01 19:16:29 +00:00
|
|
|
if (MachineInstr *NewDV =
|
2010-08-04 18:42:02 +00:00
|
|
|
TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
|
|
|
|
MachineBasicBlock *MBB = DBG->getParent();
|
|
|
|
MBB->insert(MI, NewDV);
|
|
|
|
DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
|
|
|
|
}
|
|
|
|
}
|
2011-06-21 23:02:36 +00:00
|
|
|
// Now this register is spilled there is should not be any DBG_VALUE pointing
|
|
|
|
// to this register because they are all pointing to spilled value now.
|
|
|
|
LRIDbgValues.clear();
|
2010-05-17 02:49:15 +00:00
|
|
|
if (SpillKill)
|
2010-05-11 23:24:47 +00:00
|
|
|
LR.LastUse = 0; // Don't kill register again
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-05-17 02:49:15 +00:00
|
|
|
killVirtReg(LRI);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// spillAll - Spill all dirty virtregs without killing them.
|
2010-05-17 02:07:22 +00:00
|
|
|
void RAFast::spillAll(MachineInstr *MI) {
|
2010-05-17 15:30:37 +00:00
|
|
|
if (LiveVirtRegs.empty()) return;
|
2010-05-17 02:07:32 +00:00
|
|
|
isBulkSpilling = true;
|
2010-05-17 20:01:22 +00:00
|
|
|
// The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
|
|
|
|
// of spilling here is deterministic, if arbitrary.
|
|
|
|
for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
|
|
|
|
i != e; ++i)
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, i);
|
|
|
|
LiveVirtRegs.clear();
|
|
|
|
isBulkSpilling = false;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
/// usePhysReg - Handle the direct use of a physical register.
|
|
|
|
/// Check that the register is not used by a virtreg.
|
|
|
|
/// Kill the physreg, marking it free.
|
|
|
|
/// This may add implicit kills to MO->getParent() and invalidate MO.
|
|
|
|
void RAFast::usePhysReg(MachineOperand &MO) {
|
|
|
|
unsigned PhysReg = MO.getReg();
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
|
|
|
|
"Bad usePhysReg operand");
|
|
|
|
|
|
|
|
switch (PhysRegState[PhysReg]) {
|
2010-05-11 18:54:45 +00:00
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
|
|
|
PhysRegState[PhysReg] = regFree;
|
2010-05-14 18:03:25 +00:00
|
|
|
// Fall through
|
|
|
|
case regFree:
|
|
|
|
UsedInInstr.set(PhysReg);
|
|
|
|
MO.setIsKill();
|
2010-05-11 18:54:45 +00:00
|
|
|
return;
|
|
|
|
default:
|
2010-12-08 21:35:09 +00:00
|
|
|
// The physreg was allocated to a virtual register. That means the value we
|
2010-05-14 18:03:25 +00:00
|
|
|
// wanted has been clobbered.
|
|
|
|
llvm_unreachable("Instruction uses an allocated register");
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
// Maybe a superregister is reserved?
|
2010-05-11 18:54:45 +00:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
2010-05-14 18:03:25 +00:00
|
|
|
switch (PhysRegState[Alias]) {
|
2010-05-11 18:54:45 +00:00
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
2010-05-14 18:03:25 +00:00
|
|
|
assert(TRI->isSuperRegister(PhysReg, Alias) &&
|
|
|
|
"Instruction is not using a subregister of a reserved register");
|
|
|
|
// Leave the superregister in the working set.
|
2010-05-11 18:54:45 +00:00
|
|
|
PhysRegState[Alias] = regFree;
|
2010-05-14 18:03:25 +00:00
|
|
|
UsedInInstr.set(Alias);
|
|
|
|
MO.getParent()->addRegisterKilled(Alias, TRI, true);
|
|
|
|
return;
|
|
|
|
case regFree:
|
|
|
|
if (TRI->isSuperRegister(PhysReg, Alias)) {
|
|
|
|
// Leave the superregister in the working set.
|
|
|
|
UsedInInstr.set(Alias);
|
|
|
|
MO.getParent()->addRegisterKilled(Alias, TRI, true);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
// Some other alias was in the working set - clear it.
|
|
|
|
PhysRegState[Alias] = regDisabled;
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
2010-05-14 18:03:25 +00:00
|
|
|
llvm_unreachable("Instruction uses an alias of an allocated register");
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-14 18:03:25 +00:00
|
|
|
|
|
|
|
// All aliases are disabled, bring register into working set.
|
|
|
|
PhysRegState[PhysReg] = regFree;
|
|
|
|
UsedInInstr.set(PhysReg);
|
|
|
|
MO.setIsKill();
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
/// definePhysReg - Mark PhysReg as reserved or free after spilling any
|
|
|
|
/// virtregs. This is very similar to defineVirtReg except the physreg is
|
|
|
|
/// reserved instead of allocated.
|
2010-05-17 02:07:22 +00:00
|
|
|
void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
|
|
|
|
RegState NewState) {
|
2010-05-14 18:03:25 +00:00
|
|
|
UsedInInstr.set(PhysReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
switch (unsigned VirtReg = PhysRegState[PhysReg]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
2010-05-14 18:03:25 +00:00
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, VirtReg);
|
2010-05-14 18:03:25 +00:00
|
|
|
// Fall through.
|
2010-05-11 18:54:45 +00:00
|
|
|
case regFree:
|
|
|
|
case regReserved:
|
2010-05-14 18:03:25 +00:00
|
|
|
PhysRegState[PhysReg] = NewState;
|
2010-05-11 18:54:45 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
// This is a disabled register, disable all aliases.
|
|
|
|
PhysRegState[PhysReg] = NewState;
|
2010-05-11 18:54:45 +00:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
|
|
|
switch (unsigned VirtReg = PhysRegState[Alias]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
default:
|
2010-05-17 02:07:32 +00:00
|
|
|
spillVirtReg(MI, VirtReg);
|
2010-05-14 18:03:25 +00:00
|
|
|
// Fall through.
|
|
|
|
case regFree:
|
|
|
|
case regReserved:
|
|
|
|
PhysRegState[Alias] = regDisabled;
|
|
|
|
if (TRI->isSuperRegister(PhysReg, Alias))
|
|
|
|
return;
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-14 18:03:25 +00:00
|
|
|
|
2010-05-17 15:30:32 +00:00
|
|
|
// calcSpillCost - Return the cost of spilling clearing out PhysReg and
|
|
|
|
// aliases so it is free for allocation.
|
|
|
|
// Returns 0 when PhysReg is free or disabled with all aliases disabled - it
|
|
|
|
// can be allocated directly.
|
|
|
|
// Returns spillImpossible when PhysReg or an alias can't be spilled.
|
|
|
|
unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
|
2011-04-12 22:17:44 +00:00
|
|
|
if (UsedInInstr.test(PhysReg)) {
|
2011-06-28 17:24:32 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
|
2010-05-17 21:02:08 +00:00
|
|
|
return spillImpossible;
|
2011-04-12 22:17:44 +00:00
|
|
|
}
|
2010-05-17 15:30:32 +00:00
|
|
|
switch (unsigned VirtReg = PhysRegState[PhysReg]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regFree:
|
|
|
|
return 0;
|
|
|
|
case regReserved:
|
2011-06-28 17:24:32 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
|
|
|
|
<< PrintReg(PhysReg, TRI) << " is reserved already.\n");
|
2010-05-17 15:30:32 +00:00
|
|
|
return spillImpossible;
|
|
|
|
default:
|
|
|
|
return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
|
|
|
|
}
|
|
|
|
|
2011-04-12 00:48:08 +00:00
|
|
|
// This is a disabled register, add up cost of aliases.
|
2011-06-28 17:24:32 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
|
2010-05-17 15:30:32 +00:00
|
|
|
unsigned Cost = 0;
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(PhysReg);
|
|
|
|
unsigned Alias = *AS; ++AS) {
|
2011-04-13 00:20:59 +00:00
|
|
|
if (UsedInInstr.test(Alias))
|
|
|
|
return spillImpossible;
|
2010-05-17 15:30:32 +00:00
|
|
|
switch (unsigned VirtReg = PhysRegState[Alias]) {
|
|
|
|
case regDisabled:
|
|
|
|
break;
|
|
|
|
case regFree:
|
|
|
|
++Cost;
|
|
|
|
break;
|
|
|
|
case regReserved:
|
|
|
|
return spillImpossible;
|
|
|
|
default:
|
|
|
|
Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return Cost;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-04-21 18:02:42 +00:00
|
|
|
/// assignVirtToPhysReg - This method updates local state so that we know
|
|
|
|
/// that PhysReg is the proper container for VirtReg now. The physical
|
|
|
|
/// register must not be used for anything else when this is called.
|
|
|
|
///
|
2010-05-17 02:07:29 +00:00
|
|
|
void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to "
|
|
|
|
<< PrintReg(PhysReg, TRI) << "\n");
|
2010-05-17 02:07:29 +00:00
|
|
|
PhysRegState[PhysReg] = LRE.first;
|
|
|
|
assert(!LRE.second.PhysReg && "Already assigned a physreg");
|
|
|
|
LRE.second.PhysReg = PhysReg;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// allocVirtReg - Allocate a physical register for VirtReg.
|
2010-05-17 02:07:29 +00:00
|
|
|
void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
|
|
|
|
const unsigned VirtReg = LRE.first;
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Can only allocate virtual registers");
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
// Ignore invalid hints.
|
|
|
|
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
|
2011-06-02 23:41:40 +00:00
|
|
|
!RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
|
2010-05-13 00:19:43 +00:00
|
|
|
Hint = 0;
|
|
|
|
|
|
|
|
// Take hint when possible.
|
|
|
|
if (Hint) {
|
2011-06-13 03:26:46 +00:00
|
|
|
// Ignore the hint if we would have to spill a dirty register.
|
|
|
|
unsigned Cost = calcSpillCost(Hint);
|
|
|
|
if (Cost < spillDirty) {
|
|
|
|
if (Cost)
|
|
|
|
definePhysReg(MI, Hint, regFree);
|
2010-05-17 02:07:29 +00:00
|
|
|
return assignVirtToPhysReg(LRE, Hint);
|
2010-05-13 00:19:43 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-02 18:35:30 +00:00
|
|
|
ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
|
2010-05-17 15:30:32 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// First try to find a completely free register.
|
2011-06-02 18:35:30 +00:00
|
|
|
for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
|
2010-05-11 18:54:45 +00:00
|
|
|
unsigned PhysReg = *I;
|
2011-06-02 18:35:30 +00:00
|
|
|
if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
|
2010-05-17 15:30:32 +00:00
|
|
|
return assignVirtToPhysReg(LRE, PhysReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
|
|
|
|
<< RC->getName() << "\n");
|
2010-05-17 15:30:32 +00:00
|
|
|
|
|
|
|
unsigned BestReg = 0, BestCost = spillImpossible;
|
2011-06-02 18:35:30 +00:00
|
|
|
for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
|
2010-05-17 15:30:32 +00:00
|
|
|
unsigned Cost = calcSpillCost(*I);
|
2011-06-28 17:24:32 +00:00
|
|
|
DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
|
2011-04-12 22:17:44 +00:00
|
|
|
DEBUG(dbgs() << "\tCost: " << Cost << "\n");
|
|
|
|
DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
|
2010-05-17 15:30:37 +00:00
|
|
|
// Cost is 0 when all aliases are already disabled.
|
|
|
|
if (Cost == 0)
|
|
|
|
return assignVirtToPhysReg(LRE, *I);
|
|
|
|
if (Cost < BestCost)
|
|
|
|
BestReg = *I, BestCost = Cost;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
if (BestReg) {
|
2010-05-17 15:30:37 +00:00
|
|
|
definePhysReg(MI, BestReg, regFree);
|
2010-05-17 02:07:29 +00:00
|
|
|
return assignVirtToPhysReg(LRE, BestReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2011-07-02 07:17:37 +00:00
|
|
|
// Nothing we can do. Report an error and keep going with a bad allocation.
|
|
|
|
MI->emitError("ran out of registers during register allocation");
|
|
|
|
definePhysReg(MI, *AO.begin(), regFree);
|
|
|
|
assignVirtToPhysReg(LRE, *AO.begin());
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
|
2010-05-17 03:26:09 +00:00
|
|
|
RAFast::LiveRegMap::iterator
|
|
|
|
RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
|
|
|
|
unsigned VirtReg, unsigned Hint) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Not a virtual register");
|
2010-05-17 02:49:15 +00:00
|
|
|
LiveRegMap::iterator LRI;
|
2010-05-17 02:07:29 +00:00
|
|
|
bool New;
|
2010-05-17 02:49:15 +00:00
|
|
|
tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
|
|
|
|
LiveReg &LR = LRI->second;
|
2010-05-17 04:50:57 +00:00
|
|
|
if (New) {
|
|
|
|
// If there is no hint, peek at the only use of this register.
|
|
|
|
if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
|
|
|
|
MRI->hasOneNonDBGUse(VirtReg)) {
|
2010-07-03 00:04:37 +00:00
|
|
|
const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
|
2010-05-17 04:50:57 +00:00
|
|
|
// It's a copy, use the destination register as a hint.
|
2010-07-03 00:04:37 +00:00
|
|
|
if (UseMI.isCopyLike())
|
|
|
|
Hint = UseMI.getOperand(0).getReg();
|
2010-05-17 04:50:57 +00:00
|
|
|
}
|
2010-05-17 02:49:15 +00:00
|
|
|
allocVirtReg(MI, *LRI, Hint);
|
2010-06-29 19:15:30 +00:00
|
|
|
} else if (LR.LastUse) {
|
2010-05-18 21:10:50 +00:00
|
|
|
// Redefining a live register - kill at the last use, unless it is this
|
|
|
|
// instruction defining VirtReg multiple times.
|
|
|
|
if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
|
|
|
|
addKillFlag(LR);
|
|
|
|
}
|
2010-05-17 02:07:29 +00:00
|
|
|
assert(LR.PhysReg && "Register not assigned");
|
2010-05-11 23:24:47 +00:00
|
|
|
LR.LastUse = MI;
|
|
|
|
LR.LastOpNum = OpNum;
|
|
|
|
LR.Dirty = true;
|
|
|
|
UsedInInstr.set(LR.PhysReg);
|
2010-05-17 03:26:09 +00:00
|
|
|
return LRI;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
|
2010-05-17 03:26:09 +00:00
|
|
|
RAFast::LiveRegMap::iterator
|
|
|
|
RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
|
|
|
|
unsigned VirtReg, unsigned Hint) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
|
|
|
"Not a virtual register");
|
2010-05-17 02:49:15 +00:00
|
|
|
LiveRegMap::iterator LRI;
|
2010-05-17 02:07:29 +00:00
|
|
|
bool New;
|
2010-05-17 02:49:15 +00:00
|
|
|
tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
|
|
|
|
LiveReg &LR = LRI->second;
|
2010-05-17 03:26:06 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(OpNum);
|
2010-05-17 02:07:29 +00:00
|
|
|
if (New) {
|
2010-05-17 02:49:15 +00:00
|
|
|
allocVirtReg(MI, *LRI, Hint);
|
2010-05-13 00:19:43 +00:00
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
2010-05-11 18:54:45 +00:00
|
|
|
int FrameIndex = getStackSpaceFor(VirtReg, RC);
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
|
|
|
|
<< PrintReg(LR.PhysReg, TRI) << "\n");
|
2010-05-17 02:07:29 +00:00
|
|
|
TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
|
2010-05-11 18:54:45 +00:00
|
|
|
++NumLoads;
|
2010-05-17 02:07:29 +00:00
|
|
|
} else if (LR.Dirty) {
|
2010-05-15 06:09:08 +00:00
|
|
|
if (isLastUseOfLocalReg(MO)) {
|
|
|
|
DEBUG(dbgs() << "Killing last use: " << MO << "\n");
|
2010-06-29 19:15:30 +00:00
|
|
|
if (MO.isUse())
|
|
|
|
MO.setIsKill();
|
|
|
|
else
|
|
|
|
MO.setIsDead();
|
2010-05-15 06:09:08 +00:00
|
|
|
} else if (MO.isKill()) {
|
|
|
|
DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
|
|
|
|
MO.setIsKill(false);
|
2010-06-29 19:15:30 +00:00
|
|
|
} else if (MO.isDead()) {
|
|
|
|
DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
|
|
|
|
MO.setIsDead(false);
|
2010-05-15 06:09:08 +00:00
|
|
|
}
|
2010-05-17 03:26:06 +00:00
|
|
|
} else if (MO.isKill()) {
|
|
|
|
// We must remove kill flags from uses of reloaded registers because the
|
|
|
|
// register would be killed immediately, and there might be a second use:
|
|
|
|
// %foo = OR %x<kill>, %x
|
|
|
|
// This would cause a second reload of %x into a different register.
|
|
|
|
DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
|
|
|
|
MO.setIsKill(false);
|
2010-06-29 19:15:30 +00:00
|
|
|
} else if (MO.isDead()) {
|
|
|
|
DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
|
|
|
|
MO.setIsDead(false);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-17 02:07:29 +00:00
|
|
|
assert(LR.PhysReg && "Register not assigned");
|
2010-05-11 23:24:47 +00:00
|
|
|
LR.LastUse = MI;
|
|
|
|
LR.LastOpNum = OpNum;
|
|
|
|
UsedInInstr.set(LR.PhysReg);
|
2010-05-17 03:26:09 +00:00
|
|
|
return LRI;
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-18 21:10:50 +00:00
|
|
|
// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
|
|
|
|
// subregs. This may invalidate any operand pointers.
|
|
|
|
// Return true if the operand kills its register.
|
|
|
|
bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
|
|
|
|
MachineOperand &MO = MI->getOperand(OpNum);
|
2010-05-17 02:49:21 +00:00
|
|
|
if (!MO.getSubReg()) {
|
2010-05-11 18:54:45 +00:00
|
|
|
MO.setReg(PhysReg);
|
2010-05-17 02:49:21 +00:00
|
|
|
return MO.isKill() || MO.isDead();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle subregister index.
|
|
|
|
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
|
|
|
|
MO.setSubReg(0);
|
2010-05-19 21:36:05 +00:00
|
|
|
|
|
|
|
// A kill flag implies killing the full register. Add corresponding super
|
|
|
|
// register kill.
|
|
|
|
if (MO.isKill()) {
|
|
|
|
MI->addRegisterKilled(PhysReg, TRI, true);
|
2010-05-17 02:49:21 +00:00
|
|
|
return true;
|
|
|
|
}
|
2010-05-19 21:36:05 +00:00
|
|
|
return MO.isDead();
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-06-28 18:34:34 +00:00
|
|
|
// Handle special instruction operand like early clobbers and tied ops when
|
|
|
|
// there are additional physreg defines.
|
|
|
|
void RAFast::handleThroughOperands(MachineInstr *MI,
|
|
|
|
SmallVectorImpl<unsigned> &VirtDead) {
|
|
|
|
DEBUG(dbgs() << "Scanning for through registers:");
|
|
|
|
SmallSet<unsigned, 8> ThroughRegs;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2011-01-10 02:58:51 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
|
|
continue;
|
2010-06-29 19:15:30 +00:00
|
|
|
if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
|
|
|
|
(MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
|
2010-06-28 18:34:34 +00:00
|
|
|
if (ThroughRegs.insert(Reg))
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << ' ' << PrintReg(Reg));
|
2010-06-28 18:34:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If any physreg defines collide with preallocated through registers,
|
|
|
|
// we must spill and reallocate.
|
|
|
|
DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg() || !MO.isDef()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
|
|
|
UsedInInstr.set(Reg);
|
|
|
|
if (ThroughRegs.count(PhysRegState[Reg]))
|
|
|
|
definePhysReg(MI, Reg, regFree);
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
|
|
|
|
UsedInInstr.set(*AS);
|
|
|
|
if (ThroughRegs.count(PhysRegState[*AS]))
|
|
|
|
definePhysReg(MI, *AS, regFree);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-29 19:15:30 +00:00
|
|
|
SmallVector<unsigned, 8> PartialDefs;
|
2011-11-22 06:27:18 +00:00
|
|
|
DEBUG(dbgs() << "Allocating tied uses.\n");
|
2010-06-28 18:34:34 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2011-01-10 02:58:51 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
2010-06-28 18:34:34 +00:00
|
|
|
if (MO.isUse()) {
|
|
|
|
unsigned DefIdx = 0;
|
|
|
|
if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
|
|
|
|
DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
|
|
|
|
<< DefIdx << ".\n");
|
|
|
|
LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
|
|
|
setPhysReg(MI, i, PhysReg);
|
2010-06-29 19:15:30 +00:00
|
|
|
// Note: we don't update the def operand yet. That would cause the normal
|
|
|
|
// def-scan to attempt spilling.
|
|
|
|
} else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
|
|
|
|
DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
|
|
|
|
// Reload the register, but don't assign to the operand just yet.
|
|
|
|
// That would confuse the later phys-def processing pass.
|
|
|
|
LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
|
|
|
|
PartialDefs.push_back(LRI->second.PhysReg);
|
2010-06-28 18:34:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-22 06:27:18 +00:00
|
|
|
DEBUG(dbgs() << "Allocating early clobbers.\n");
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
|
|
|
if (!MO.isEarlyClobber())
|
|
|
|
continue;
|
|
|
|
// Note: defineVirtReg may invalidate MO.
|
|
|
|
LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
|
|
|
if (setPhysReg(MI, i, PhysReg))
|
|
|
|
VirtDead.push_back(Reg);
|
|
|
|
}
|
|
|
|
|
2010-06-28 18:34:34 +00:00
|
|
|
// Restore UsedInInstr to a state usable for allocating normal virtual uses.
|
2010-09-03 21:45:15 +00:00
|
|
|
UsedInInstr.reset();
|
2010-06-28 18:34:34 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
2011-06-28 17:24:32 +00:00
|
|
|
DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
|
|
|
|
<< " as used in instr\n");
|
2010-06-28 18:34:34 +00:00
|
|
|
UsedInInstr.set(Reg);
|
|
|
|
}
|
2010-06-29 19:15:30 +00:00
|
|
|
|
|
|
|
// Also mark PartialDefs as used to avoid reallocation.
|
|
|
|
for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
|
|
|
|
UsedInInstr.set(PartialDefs[i]);
|
2010-06-28 18:34:34 +00:00
|
|
|
}
|
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
void RAFast::AllocateBasicBlock() {
|
|
|
|
DEBUG(dbgs() << "\nAllocating " << *MBB);
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2011-02-04 22:44:08 +00:00
|
|
|
// FIXME: This should probably be added by instruction selection instead?
|
|
|
|
// If the last instruction in the block is a return, make sure to mark it as
|
|
|
|
// using all of the live-out values in the function. Things marked both call
|
|
|
|
// and return are tail calls; do not do this for them. The tail callee need
|
|
|
|
// not take the same registers as input that it produces as output, and there
|
|
|
|
// are dependencies for its input registers elsewhere.
|
2011-12-07 07:15:52 +00:00
|
|
|
if (!MBB->empty() && MBB->back().isReturn() &&
|
|
|
|
!MBB->back().isCall()) {
|
2011-02-04 22:44:08 +00:00
|
|
|
MachineInstr *Ret = &MBB->back();
|
|
|
|
|
|
|
|
for (MachineRegisterInfo::liveout_iterator
|
|
|
|
I = MF->getRegInfo().liveout_begin(),
|
|
|
|
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
|
|
|
|
"Cannot have a live-out virtual register.");
|
|
|
|
|
|
|
|
// Add live-out registers as implicit uses.
|
|
|
|
Ret->addRegisterKilled(*I, TRI, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
PhysRegState.assign(TRI->getNumRegs(), regDisabled);
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
MachineBasicBlock::iterator MII = MBB->begin();
|
2010-05-11 18:54:45 +00:00
|
|
|
|
|
|
|
// Add live-in registers as live.
|
2010-05-17 02:07:22 +00:00
|
|
|
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
|
|
|
|
E = MBB->livein_end(); I != E; ++I)
|
2011-06-02 23:41:40 +00:00
|
|
|
if (RegClassInfo.isAllocatable(*I))
|
2010-08-31 19:54:25 +00:00
|
|
|
definePhysReg(MII, *I, regReserved);
|
2010-05-11 18:54:45 +00:00
|
|
|
|
2010-06-28 18:34:34 +00:00
|
|
|
SmallVector<unsigned, 8> VirtDead;
|
2010-05-14 04:30:51 +00:00
|
|
|
SmallVector<MachineInstr*, 32> Coalesced;
|
2010-04-21 18:02:42 +00:00
|
|
|
|
|
|
|
// Otherwise, sequentially allocate each instruction in the MBB.
|
2010-05-17 02:07:22 +00:00
|
|
|
while (MII != MBB->end()) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineInstr *MI = MII++;
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
2010-04-21 18:02:42 +00:00
|
|
|
DEBUG({
|
2010-05-13 20:43:17 +00:00
|
|
|
dbgs() << "\n>> " << *MI << "Regs:";
|
2010-05-11 18:54:45 +00:00
|
|
|
for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
|
|
|
|
if (PhysRegState[Reg] == regDisabled) continue;
|
|
|
|
dbgs() << " " << TRI->getName(Reg);
|
|
|
|
switch(PhysRegState[Reg]) {
|
|
|
|
case regFree:
|
|
|
|
break;
|
|
|
|
case regReserved:
|
2010-05-13 20:43:17 +00:00
|
|
|
dbgs() << "*";
|
2010-05-11 18:54:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
2011-01-09 03:05:53 +00:00
|
|
|
dbgs() << '=' << PrintReg(PhysRegState[Reg]);
|
2010-05-11 23:24:47 +00:00
|
|
|
if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
|
2010-05-11 18:54:45 +00:00
|
|
|
dbgs() << "*";
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
|
2010-05-11 18:54:45 +00:00
|
|
|
"Bad inverse map");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
dbgs() << '\n';
|
2010-05-11 23:24:45 +00:00
|
|
|
// Check that LiveVirtRegs is the inverse.
|
|
|
|
for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
|
|
|
|
e = LiveVirtRegs.end(); i != e; ++i) {
|
2010-05-11 18:54:45 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
|
|
|
|
"Bad map key");
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
|
2010-05-11 18:54:45 +00:00
|
|
|
"Bad map value");
|
2010-05-11 23:24:45 +00:00
|
|
|
assert(PhysRegState[i->second.PhysReg] == i->first &&
|
|
|
|
"Bad inverse map");
|
2010-05-11 18:54:45 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
});
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Debug values are not allowed to change codegen in any way.
|
|
|
|
if (MI->isDebugValue()) {
|
2010-07-19 23:25:39 +00:00
|
|
|
bool ScanDbgValue = true;
|
|
|
|
while (ScanDbgValue) {
|
|
|
|
ScanDbgValue = false;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2011-01-10 02:58:51 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
2010-07-19 23:25:39 +00:00
|
|
|
LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
|
|
|
|
if (LRI != LiveVirtRegs.end())
|
|
|
|
setPhysReg(MI, i, LRI->second.PhysReg);
|
2010-07-09 21:48:31 +00:00
|
|
|
else {
|
2010-07-19 23:25:39 +00:00
|
|
|
int SS = StackSlotForVirtReg[Reg];
|
2010-09-10 20:32:09 +00:00
|
|
|
if (SS == -1) {
|
2010-09-01 19:16:29 +00:00
|
|
|
// We can't allocate a physreg for a DebugValue, sorry!
|
2010-09-10 20:32:09 +00:00
|
|
|
DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
|
2010-09-01 19:16:29 +00:00
|
|
|
MO.setReg(0);
|
2010-09-10 20:32:09 +00:00
|
|
|
}
|
2010-07-19 23:25:39 +00:00
|
|
|
else {
|
|
|
|
// Modify DBG_VALUE now that the value is in a spill slot.
|
2010-08-04 18:42:02 +00:00
|
|
|
int64_t Offset = MI->getOperand(1).getImm();
|
2010-09-01 19:16:29 +00:00
|
|
|
const MDNode *MDPtr =
|
2010-07-19 23:25:39 +00:00
|
|
|
MI->getOperand(MI->getNumOperands()-1).getMetadata();
|
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
2010-09-01 19:16:29 +00:00
|
|
|
if (MachineInstr *NewDV =
|
2010-07-19 23:25:39 +00:00
|
|
|
TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
|
2010-09-01 19:16:29 +00:00
|
|
|
DEBUG(dbgs() << "Modifying debug info due to spill:" <<
|
|
|
|
"\t" << *MI);
|
2010-07-19 23:25:39 +00:00
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
MBB->insert(MBB->erase(MI), NewDV);
|
|
|
|
// Scan NewDV operands from the beginning.
|
|
|
|
MI = NewDV;
|
|
|
|
ScanDbgValue = true;
|
|
|
|
break;
|
2010-09-10 20:32:09 +00:00
|
|
|
} else {
|
2010-09-01 19:16:29 +00:00
|
|
|
// We can't allocate a physreg for a DebugValue; sorry!
|
2010-09-10 20:32:09 +00:00
|
|
|
DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
|
2010-09-01 19:16:29 +00:00
|
|
|
MO.setReg(0);
|
2010-09-10 20:32:09 +00:00
|
|
|
}
|
2010-07-19 23:25:39 +00:00
|
|
|
}
|
2010-07-09 21:48:31 +00:00
|
|
|
}
|
2011-11-15 21:03:58 +00:00
|
|
|
LiveDbgValueMap[Reg].push_back(MI);
|
2010-07-09 21:48:31 +00:00
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-11 18:54:45 +00:00
|
|
|
// Next instruction.
|
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
// If this is a copy, we may be able to coalesce.
|
2010-07-16 04:45:42 +00:00
|
|
|
unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
|
2010-07-03 00:04:37 +00:00
|
|
|
if (MI->isCopy()) {
|
|
|
|
CopyDst = MI->getOperand(0).getReg();
|
|
|
|
CopySrc = MI->getOperand(1).getReg();
|
|
|
|
CopyDstSub = MI->getOperand(0).getSubReg();
|
|
|
|
CopySrcSub = MI->getOperand(1).getSubReg();
|
2010-07-16 04:45:42 +00:00
|
|
|
}
|
2010-05-13 00:19:43 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Track registers used by instruction.
|
2010-09-03 21:45:15 +00:00
|
|
|
UsedInInstr.reset();
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// First scan.
|
|
|
|
// Mark physreg uses and early clobbers as used.
|
2010-05-14 21:55:52 +00:00
|
|
|
// Find the end of the virtreg operands
|
|
|
|
unsigned VirtOpEnd = 0;
|
2010-06-29 19:15:30 +00:00
|
|
|
bool hasTiedOps = false;
|
|
|
|
bool hasEarlyClobbers = false;
|
|
|
|
bool hasPartialRedefs = false;
|
|
|
|
bool hasPhysDefs = false;
|
2010-05-11 18:54:45 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2010-05-14 21:55:52 +00:00
|
|
|
if (!Reg) continue;
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
|
VirtOpEnd = i+1;
|
2010-06-29 19:15:30 +00:00
|
|
|
if (MO.isUse()) {
|
2010-06-28 18:34:34 +00:00
|
|
|
hasTiedOps = hasTiedOps ||
|
2011-06-28 19:10:37 +00:00
|
|
|
MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
|
2010-06-29 19:15:30 +00:00
|
|
|
} else {
|
|
|
|
if (MO.isEarlyClobber())
|
|
|
|
hasEarlyClobbers = true;
|
|
|
|
if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
|
|
|
|
hasPartialRedefs = true;
|
|
|
|
}
|
2010-05-14 21:55:52 +00:00
|
|
|
continue;
|
|
|
|
}
|
2011-06-02 23:41:40 +00:00
|
|
|
if (!RegClassInfo.isAllocatable(Reg)) continue;
|
2010-05-11 18:54:45 +00:00
|
|
|
if (MO.isUse()) {
|
2010-05-14 18:03:25 +00:00
|
|
|
usePhysReg(MO);
|
2010-05-11 18:54:45 +00:00
|
|
|
} else if (MO.isEarlyClobber()) {
|
2010-06-15 16:20:57 +00:00
|
|
|
definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
|
|
|
|
regFree : regReserved);
|
2010-06-28 18:34:34 +00:00
|
|
|
hasEarlyClobbers = true;
|
|
|
|
} else
|
|
|
|
hasPhysDefs = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// The instruction may have virtual register operands that must be allocated
|
|
|
|
// the same register at use-time and def-time: early clobbers and tied
|
|
|
|
// operands. If there are also physical defs, these registers must avoid
|
|
|
|
// both physical defs and uses, making them more constrained than normal
|
|
|
|
// operands.
|
2010-09-01 19:16:29 +00:00
|
|
|
// Similarly, if there are multiple defs and tied operands, we must make
|
|
|
|
// sure the same register is allocated to uses and defs.
|
2010-06-28 18:34:34 +00:00
|
|
|
// We didn't detect inline asm tied operands above, so just make this extra
|
|
|
|
// pass for all inline asm.
|
2010-06-29 19:15:30 +00:00
|
|
|
if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
|
2011-06-28 19:10:37 +00:00
|
|
|
(hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
|
2010-06-28 18:34:34 +00:00
|
|
|
handleThroughOperands(MI, VirtDead);
|
|
|
|
// Don't attempt coalescing when we have funny stuff going on.
|
|
|
|
CopyDst = 0;
|
2010-07-29 00:52:19 +00:00
|
|
|
// Pretend we have early clobbers so the use operands get marked below.
|
|
|
|
// This is not necessary for the common case of a single tied use.
|
|
|
|
hasEarlyClobbers = true;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Second scan.
|
2010-06-28 18:34:34 +00:00
|
|
|
// Allocate virtreg uses.
|
2010-05-14 21:55:52 +00:00
|
|
|
for (unsigned i = 0; i != VirtOpEnd; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-05-11 18:54:45 +00:00
|
|
|
if (!MO.isReg()) continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
2011-01-10 02:58:51 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
2010-05-11 18:54:45 +00:00
|
|
|
if (MO.isUse()) {
|
2010-05-17 03:26:09 +00:00
|
|
|
LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
2010-05-14 04:30:51 +00:00
|
|
|
CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
|
2010-05-18 21:10:50 +00:00
|
|
|
if (setPhysReg(MI, i, PhysReg))
|
2010-05-17 03:26:09 +00:00
|
|
|
killVirtReg(LRI);
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->addPhysRegsUsed(UsedInInstr);
|
2010-05-11 20:30:28 +00:00
|
|
|
|
2010-07-29 00:52:19 +00:00
|
|
|
// Track registers defined by instruction - early clobbers and tied uses at
|
|
|
|
// this point.
|
2010-09-03 21:45:15 +00:00
|
|
|
UsedInInstr.reset();
|
2010-06-28 18:34:34 +00:00
|
|
|
if (hasEarlyClobbers) {
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-07-29 00:52:19 +00:00
|
|
|
if (!MO.isReg()) continue;
|
2010-06-28 18:34:34 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
2010-07-29 00:52:19 +00:00
|
|
|
// Look for physreg defs and tied uses.
|
|
|
|
if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
|
2010-06-28 18:34:34 +00:00
|
|
|
UsedInInstr.set(Reg);
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
|
|
|
|
UsedInInstr.set(*AS);
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-17 02:49:18 +00:00
|
|
|
unsigned DefOpEnd = MI->getNumOperands();
|
2011-12-07 07:15:52 +00:00
|
|
|
if (MI->isCall()) {
|
2010-05-17 02:49:18 +00:00
|
|
|
// Spill all virtregs before a call. This serves two purposes: 1. If an
|
2010-09-01 19:16:29 +00:00
|
|
|
// exception is thrown, the landing pad is going to expect to find
|
|
|
|
// registers in their spill slots, and 2. we don't have to wade through
|
|
|
|
// all the <imp-def> operands on the call instruction.
|
2010-05-17 02:49:18 +00:00
|
|
|
DefOpEnd = VirtOpEnd;
|
|
|
|
DEBUG(dbgs() << " Spilling remaining registers before call.\n");
|
|
|
|
spillAll(MI);
|
2010-06-04 18:08:29 +00:00
|
|
|
|
|
|
|
// The imp-defs are skipped below, but we still need to mark those
|
|
|
|
// registers as used by the function.
|
2011-06-28 19:10:37 +00:00
|
|
|
SkippedInstrs.insert(&MCID);
|
2010-05-17 02:49:18 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Third scan.
|
|
|
|
// Allocate defs and collect dead defs.
|
2010-05-17 02:49:18 +00:00
|
|
|
for (unsigned i = 0; i != DefOpEnd; ++i) {
|
2010-04-21 18:02:42 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2010-06-15 16:20:57 +00:00
|
|
|
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
|
|
|
|
continue;
|
2010-05-11 18:54:45 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
2011-06-02 23:41:40 +00:00
|
|
|
if (!RegClassInfo.isAllocatable(Reg)) continue;
|
2010-05-17 02:07:22 +00:00
|
|
|
definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
|
|
|
|
regFree : regReserved);
|
2010-05-11 18:54:45 +00:00
|
|
|
continue;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
2010-05-17 03:26:09 +00:00
|
|
|
LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
|
|
|
|
unsigned PhysReg = LRI->second.PhysReg;
|
2010-05-18 21:10:50 +00:00
|
|
|
if (setPhysReg(MI, i, PhysReg)) {
|
|
|
|
VirtDead.push_back(Reg);
|
2010-05-14 04:30:51 +00:00
|
|
|
CopyDst = 0; // cancel coalescing;
|
|
|
|
} else
|
|
|
|
CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-18 21:10:50 +00:00
|
|
|
// Kill dead defs after the scan to ensure that multiple defs of the same
|
|
|
|
// register are allocated identically. We didn't need to do this for uses
|
|
|
|
// because we are crerating our own kill flags, and they are always at the
|
|
|
|
// last use.
|
|
|
|
for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
|
|
|
|
killVirtReg(VirtDead[i]);
|
|
|
|
VirtDead.clear();
|
|
|
|
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->addPhysRegsUsed(UsedInInstr);
|
2010-05-13 20:43:17 +00:00
|
|
|
|
2010-05-14 04:30:51 +00:00
|
|
|
if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
|
|
|
|
DEBUG(dbgs() << "-- coalescing: " << *MI);
|
|
|
|
Coalesced.push_back(MI);
|
|
|
|
} else {
|
|
|
|
DEBUG(dbgs() << "<< " << *MI);
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
2010-05-11 18:54:45 +00:00
|
|
|
// Spill all physical registers holding virtual registers now.
|
2010-05-17 02:07:32 +00:00
|
|
|
DEBUG(dbgs() << "Spilling live registers at end of block.\n");
|
|
|
|
spillAll(MBB->getFirstTerminator());
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-14 04:30:51 +00:00
|
|
|
// Erase all the coalesced copies. We are delaying it until now because
|
2010-05-17 02:07:32 +00:00
|
|
|
// LiveVirtRegs might refer to the instrs.
|
2010-05-14 04:30:51 +00:00
|
|
|
for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
|
2010-05-17 02:07:22 +00:00
|
|
|
MBB->erase(Coalesced[i]);
|
2010-05-14 21:55:50 +00:00
|
|
|
NumCopies += Coalesced.size();
|
2010-05-14 04:30:51 +00:00
|
|
|
|
2010-05-17 02:07:22 +00:00
|
|
|
DEBUG(MBB->dump());
|
2010-04-21 18:02:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// runOnMachineFunction - Register allocate the whole function
|
|
|
|
///
|
|
|
|
bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
|
2010-05-13 20:43:17 +00:00
|
|
|
DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
|
|
|
|
<< "********** Function: "
|
|
|
|
<< ((Value*)Fn.getFunction())->getName() << '\n');
|
2010-04-21 18:02:42 +00:00
|
|
|
MF = &Fn;
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI = &MF->getRegInfo();
|
2010-04-21 18:02:42 +00:00
|
|
|
TM = &Fn.getTarget();
|
|
|
|
TRI = TM->getRegisterInfo();
|
|
|
|
TII = TM->getInstrInfo();
|
2012-01-05 00:26:49 +00:00
|
|
|
MRI->freezeReservedRegs(Fn);
|
2011-06-02 18:35:30 +00:00
|
|
|
RegClassInfo.runOnMachineFunction(Fn);
|
2010-04-21 18:02:42 +00:00
|
|
|
UsedInInstr.resize(TRI->getNumRegs());
|
|
|
|
|
|
|
|
// initialize the virtual->physical register map to have a 'null'
|
|
|
|
// mapping for all virtual registers
|
2011-01-09 21:58:20 +00:00
|
|
|
StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
|
2010-04-21 18:02:42 +00:00
|
|
|
|
|
|
|
// Loop over all of the basic blocks, eliminating virtual register references
|
2010-05-17 02:07:22 +00:00
|
|
|
for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
|
|
|
|
MBBi != MBBe; ++MBBi) {
|
|
|
|
MBB = &*MBBi;
|
|
|
|
AllocateBasicBlock();
|
|
|
|
}
|
2010-04-21 18:02:42 +00:00
|
|
|
|
2010-05-11 20:30:28 +00:00
|
|
|
// Make sure the set of used physregs is closed under subreg operations.
|
2010-05-13 00:19:43 +00:00
|
|
|
MRI->closePhysRegsUsed(*TRI);
|
2010-05-11 20:30:28 +00:00
|
|
|
|
2010-06-04 18:08:29 +00:00
|
|
|
// Add the clobber lists for all the instructions we skipped earlier.
|
2011-06-28 19:10:37 +00:00
|
|
|
for (SmallPtrSet<const MCInstrDesc*, 4>::const_iterator
|
2010-06-04 18:08:29 +00:00
|
|
|
I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
|
|
|
|
if (const unsigned *Defs = (*I)->getImplicitDefs())
|
|
|
|
while (*Defs)
|
|
|
|
MRI->setPhysRegUsed(*Defs++);
|
|
|
|
|
|
|
|
SkippedInstrs.clear();
|
2010-04-21 18:02:42 +00:00
|
|
|
StackSlotForVirtReg.clear();
|
2010-08-04 18:42:02 +00:00
|
|
|
LiveDbgValueMap.clear();
|
2010-04-21 18:02:42 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
FunctionPass *llvm::createFastRegisterAllocator() {
|
|
|
|
return new RAFast();
|
|
|
|
}
|