RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-24 05:09:34 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down

Browse Source 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-18 20:57:22 +00:00
parent 1360bc8eb0
commit 0e6a052331
70 changed files with 646 additions and 605 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/CodeGen/MachineModuleInfo.h
View File

@ -170,7 +170,8 @@ public:
MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL.
// Real constructor.
MachineModuleInfo(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
const TargetAsmInfo *TAI);
~MachineModuleInfo();
bool doInitialization();

9
include/llvm/MC/MCContext.h
View File

@ -26,6 +26,7 @@ namespace llvm {
class MCLabel;
class MCDwarfFile;
class MCDwarfLoc;
class MCRegisterInfo;
class MCLineSection;
class StringRef;
class Twine;
@ -46,6 +47,9 @@ namespace llvm {
/// The MCAsmInfo for this target.
const MCAsmInfo &MAI;
/// The MCRegisterInfo for this target.
const MCRegisterInfo &MRI;
const TargetAsmInfo *TAI;
/// Allocator - Allocator object used for creating machine code objects.
@ -110,11 +114,14 @@ namespace llvm {
MCSymbol *CreateSymbol(StringRef Name);
public:
explicit MCContext(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
const TargetAsmInfo *TAI);
~MCContext();
const MCAsmInfo &getAsmInfo() const { return MAI; }
const MCRegisterInfo &getRegisterInfo() const { return MRI; }
const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; }
void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; }

80
include/llvm/MC/MCRegisterInfo.h
View File

@ -16,6 +16,7 @@
#ifndef LLVM_MC_MCREGISTERINFO_H
#define LLVM_MC_MCREGISTERINFO_H
#include "llvm/ADT/DenseMap.h"
#include <cassert>
namespace llvm {
@ -51,17 +52,59 @@ struct MCRegisterDesc {
///
class MCRegisterInfo {
private:
const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
unsigned RAReg; // Return address register
DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
public:
/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR) {
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
Desc = D;
NumRegs = NR;
RAReg = RA;
}
/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
/// register number mapping. Called by TableGen auto-generated routines.
/// *DO NOT USE*.
void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
if (isEH)
EHL2DwarfRegs[LLVMReg] = DwarfReg;
else
L2DwarfRegs[LLVMReg] = DwarfReg;
}
/// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
/// register number mapping. Called by TableGen auto-generated routines.
/// *DO NOT USE*.
void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
if (isEH)
EHDwarf2LRegs[DwarfReg] = LLVMReg;
else
Dwarf2LRegs[DwarfReg] = LLVMReg;
}
/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
/// number mapping. By default the SEH register number is just the same
/// as the LLVM register number.
/// FIXME: TableGen these numbers. Currently this requires target specific
/// initialization code.
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
L2SEHRegs[LLVMReg] = SEHReg;
}
/// getRARegister - This method should return the register where the return
/// address can be found.
unsigned getRARegister() const {
return RAReg;
}
const MCRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
@ -122,6 +165,37 @@ public:
unsigned getNumRegs() const {
return NumRegs;
}
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
/// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and
/// debugging info.
int getDwarfRegNum(unsigned RegNum, bool isEH) const {
const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
if (I == M.end()) return -1;
return I->second;
}
/// getLLVMRegNum - Map a dwarf register back to a target register.
///
int getLLVMRegNum(unsigned RegNum, bool isEH) const {
const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
if (I == M.end()) {
assert(0 && "Invalid RegNum");
return -1;
}
return I->second;
}
/// getSEHRegNum - Map a target register to an equivalent SEH register
/// number. Returns LLVM register number if there is no equivalent value.
int getSEHRegNum(unsigned RegNum) const {
const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
if (I == L2SEHRegs.end()) return (int)RegNum;
return I->second;
}
};
} // End llvm namespace

21
include/llvm/Target/TargetAsmInfo.h
View File

@ -29,7 +29,6 @@ namespace llvm {
class TargetAsmInfo {
std::vector<MachineMove> InitialFrameState;
const TargetRegisterInfo *TRI;
const TargetFrameLowering *TFI;
const TargetLoweringObjectFile *TLOF;
@ -74,29 +73,9 @@ public:
return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH);
}
const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
return TRI->getCalleeSavedRegs(MF);
}
unsigned getDwarfRARegNum(bool isEH) const {
return TRI->getDwarfRegNum(TRI->getRARegister(), isEH);
}
const std::vector<MachineMove> &getInitialFrameState() const {
return InitialFrameState;
}
int getDwarfRegNum(unsigned RegNum, bool isEH) const {
return TRI->getDwarfRegNum(RegNum, isEH);
}
int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
return TRI->getLLVMRegNum(DwarfRegNum, isEH);
}
int getSEHRegNum(unsigned RegNum) const {
return TRI->getSEHRegNum(RegNum);
}
};
}

18
include/llvm/Target/TargetRegisterInfo.h
View File

@ -699,28 +699,10 @@ public:
//===--------------------------------------------------------------------===//
/// Debug information queries.
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
/// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and
/// debugging info.
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
/// getFrameRegister - This method should return the register used as a base
/// for values allocated in the current stack frame.
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
/// getRARegister - This method should return the register where the return
/// address can be found.
virtual unsigned getRARegister() const = 0;
/// getSEHRegNum - Map a target register to an equivalent SEH register
/// number. Returns -1 if there is no equivalent value.
virtual int getSEHRegNum(unsigned i) const {
return i;
}
/// getCompactUnwindRegNum - This function maps the register to the number for
/// compact unwind encoding. Return -1 if the register isn't valid.
virtual int getCompactUnwindRegNum(unsigned, bool) const {

8
include/llvm/Target/TargetRegistry.h
View File

@ -69,7 +69,7 @@ namespace llvm {
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
StringRef TT);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
StringRef CPU,
StringRef Features);
@ -263,10 +263,10 @@ namespace llvm {
/// createMCRegInfo - Create a MCRegisterInfo implementation.
///
MCRegisterInfo *createMCRegInfo() const {
MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
if (!MCRegInfoCtorFn)
return 0;
return MCRegInfoCtorFn();
return MCRegInfoCtorFn(Triple);
}
/// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
@ -803,7 +803,7 @@ namespace llvm {
TargetRegistry::RegisterMCRegInfo(T, &Allocator);
}
private:
static MCRegisterInfo *Allocator() {
static MCRegisterInfo *Allocator(StringRef TT) {
return new MCRegisterInfoImpl();
}
};

15
include/llvm/Target/TargetSelect.h
View File

@ -34,6 +34,10 @@ extern "C" {
void LLVMInitialize##TargetName##MCInstrInfo();
#include "llvm/Config/Targets.def"
#define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##MCRegisterInfo();
#include "llvm/Config/Targets.def"
#define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##MCSubtargetInfo();
#include "llvm/Config/Targets.def"
@ -98,6 +102,17 @@ namespace llvm {
#include "llvm/Config/Targets.def"
}
/// InitializeAllMCRegisterInfos - The main program should call this function
/// if it wants access to all available register infos for targets that
/// LLVM is configured to support, to make them available via the
/// TargetRegistry.
///
/// It is legal for a client to make multiple calls to this function.
inline void InitializeAllMCRegisterInfos() {
#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCRegisterInfo();
#include "llvm/Config/Targets.def"
}
/// InitializeAllMCSubtargetInfos - The main program should call this function
/// if it wants access to all available subtarget infos for targets that LLVM
/// is configured to support, to make them available via the TargetRegistry.

4
lib/CodeGen/ELFWriter.cpp
View File

@ -51,6 +51,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@ -65,7 +66,8 @@ char ELFWriter::ID = 0;
ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm)
: MachineFunctionPass(ID), O(o), TM(tm),
OutContext(*new MCContext(*TM.getMCAsmInfo(), new TargetAsmInfo(tm))),
OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(),
new TargetAsmInfo(tm))),
TLOF(TM.getTargetLowering()->getObjFileLowering()),
is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64),
isLittleEndian(TM.getTargetData()->isLittleEndian()),

3
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -370,7 +370,8 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Install a MachineModuleInfo class, which is an immutable pass that holds
// all the per-module stuff we're generating, including MCContext.
TargetAsmInfo *TAI = new TargetAsmInfo(*this);
MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI);
MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
*getRegisterInfo(), TAI);
PM.add(MMI);
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.

5
lib/CodeGen/MachineModuleInfo.cpp
View File

@ -254,8 +254,9 @@ void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) {
//===----------------------------------------------------------------------===//
MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
const MCRegisterInfo &MRI,
const TargetAsmInfo *TAI)
: ImmutablePass(ID), Context(MAI, TAI),
: ImmutablePass(ID), Context(MAI, MRI, TAI),
ObjFileMMI(0),
CurCallSite(0), CallsEHReturn(0), CallsUnwindInit(0), DbgInfoAvailable(false),
CallsExternalVAFunctionWithFloatingPointArguments(false) {
@ -267,7 +268,7 @@ MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
}
MachineModuleInfo::MachineModuleInfo()
: ImmutablePass(ID), Context(*(MCAsmInfo*)0, NULL) {
: ImmutablePass(ID), Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, NULL) {
assert(0 && "This MachineModuleInfo constructor should never be called, MMI "
"should always be explicitly constructed by LLVMTargetMachine");
abort();

5
lib/MC/MCAsmStreamer.cpp
View File

@ -15,6 +15,7 @@
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/ADT/OwningPtr.h"
@ -827,8 +828,8 @@ void MCAsmStreamer::EmitCFIEndProc() {
void MCAsmStreamer::EmitRegisterName(int64_t Register) {
if (InstPrinter && !MAI.useDwarfRegNumForCFI()) {
const TargetAsmInfo &TAI = getContext().getTargetAsmInfo();
unsigned LLVMRegister = TAI.getLLVMRegNum(Register, true);
const MCRegisterInfo &MRI = getContext().getRegisterInfo();
unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true);
InstPrinter->printRegName(OS, LLVMRegister);
} else {
OS << Register;

6
lib/MC/MCContext.cpp
View File

@ -9,6 +9,7 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSectionCOFF.h"
@ -26,8 +27,9 @@ typedef StringMap<const MCSectionELF*> ELFUniqueMapTy;
typedef StringMap<const MCSectionCOFF*> COFFUniqueMapTy;
MCContext::MCContext(const MCAsmInfo &mai, const TargetAsmInfo *tai) :
MAI(mai), TAI(tai),
MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri,
const TargetAsmInfo *tai) :
MAI(mai), MRI(mri), TAI(tai),
Allocator(), Symbols(Allocator), UsedNames(Allocator),
NextUniqueID(0),
CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0),

10
lib/MC/MCDisassembler/Disassembler.cpp
View File

@ -41,6 +41,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
llvm::InitializeAllMCAsmInfos();
llvm::InitializeAllMCRegisterInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
@ -54,6 +55,9 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(TripleName);
assert(MAI && "Unable to create target asm info!");
const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TripleName);
assert(MRI && "Unable to create target register info!");
// Package up features to be passed to target/subtarget
std::string FeaturesStr;
std::string CPU;
@ -70,7 +74,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
assert(tai && "Unable to create target assembler!");
// Set up the MCContext for creating symbols and MCExpr's.
MCContext *Ctx = new MCContext(*MAI, tai);
MCContext *Ctx = new MCContext(*MAI, *MRI, tai);
assert(Ctx && "Unable to create MCContext!");
// Set up disassembler.
@ -86,8 +90,8 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType,
GetOpInfo, SymbolLookUp,
TheTarget, MAI, TM, tai, Ctx,
DisAsm, IP);
TheTarget, MAI, MRI, TM, tai,
Ctx, DisAsm, IP);
assert(DC && "Allocation failure!");
return DC;
}

5
lib/MC/MCDisassembler/Disassembler.h
View File

@ -27,6 +27,7 @@ class MCContext;
class MCAsmInfo;
class MCDisassembler;
class MCInstPrinter;
class MCRegisterInfo;
class Target;
class TargetMachine;
@ -58,6 +59,8 @@ private:
const Target *TheTarget;
// The assembly information for the target architecture.
llvm::OwningPtr<const llvm::MCAsmInfo> MAI;
// The register information for the target architecture.
llvm::OwningPtr<const llvm::MCRegisterInfo> MRI;
// The target machine instance.
llvm::OwningPtr<llvm::TargetMachine> TM;
// The disassembler for the target architecture.
@ -76,6 +79,7 @@ public:
LLVMOpInfoCallback getOpInfo,
LLVMSymbolLookupCallback symbolLookUp,
const Target *theTarget, const MCAsmInfo *mAI,
const MCRegisterInfo *mRI,
llvm::TargetMachine *tM, const TargetAsmInfo *tai,
llvm::MCContext *ctx, const MCDisassembler *disAsm,
MCInstPrinter *iP) : TripleName(tripleName),
@ -83,6 +87,7 @@ public:
SymbolLookUp(symbolLookUp), TheTarget(theTarget), Tai(tai) {
TM.reset(tM);
MAI.reset(mAI);
MRI.reset(mRI);
Ctx.reset(ctx);
DisAsm.reset(disAsm);
IP.reset(iP);

9
lib/MC/MCDisassembler/EDDisassembler.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCParser/AsmLexer.h"
@ -108,6 +109,7 @@ void EDDisassembler::initialize() {
InitializeAllTargetInfos();
InitializeAllTargets();
InitializeAllMCAsmInfos();
InitializeAllMCRegisterInfos();
InitializeAllAsmPrinters();
InitializeAllAsmParsers();
InitializeAllDisassemblers();
@ -186,6 +188,11 @@ EDDisassembler::EDDisassembler(CPUKey &key) :
if (!AsmInfo)
return;
MRI.reset(Tgt->createMCRegInfo(tripleString));
if (!MRI)
return;
Disassembler.reset(Tgt->createMCDisassembler());
if (!Disassembler)
@ -368,7 +375,7 @@ int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands,
SourceMgr sourceMgr;
sourceMgr.setDiagHandler(diag_handler, static_cast<void*>(this));
sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
MCContext context(*AsmInfo, NULL);
MCContext context(*AsmInfo, *MRI, NULL);
OwningPtr<MCStreamer> streamer(createNullStreamer(context));
OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr,
context, *streamer,

9
lib/MC/MCDisassembler/EDDisassembler.h
View File

@ -29,22 +29,23 @@
namespace llvm {
class AsmLexer;
class AsmParser;
class AsmToken;
class MCContext;
class MCAsmInfo;
class MCAsmLexer;
class AsmParser;
class TargetAsmLexer;
class TargetAsmParser;
class MCDisassembler;
class MCInstPrinter;
class MCInst;
class MCParsedAsmOperand;
class MCRegisterInfo;
class MCStreamer;
class MCSubtargetInfo;
template <typename T> class SmallVectorImpl;
class SourceMgr;
class Target;
class TargetAsmLexer;
class TargetAsmParser;
class TargetMachine;
class TargetRegisterInfo;
@ -140,6 +141,8 @@ struct EDDisassembler {
llvm::OwningPtr<llvm::TargetMachine> TargetMachine;
/// The assembly information for the target architecture
llvm::OwningPtr<const llvm::MCAsmInfo> AsmInfo;
// The register information for the target architecture.
llvm::OwningPtr<const llvm::MCRegisterInfo> MRI;
/// The disassembler for the target architecture
llvm::OwningPtr<const llvm::MCDisassembler> Disassembler;
/// The output string for the instruction printer; must be guarded with

11
lib/MC/MCDwarf.cpp
View File

@ -485,11 +485,11 @@ static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol,
}
static const MachineLocation TranslateMachineLocation(
const TargetAsmInfo &TAI,
const MCRegisterInfo &MRI,
const MachineLocation &Loc) {
unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ?
MachineLocation::VirtualFP :
unsigned(TAI.getDwarfRegNum(Loc.getReg(), true));
unsigned(MRI.getDwarfRegNum(Loc.getReg(), true));
const MachineLocation &NewLoc = Loc.isReg() ?
MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset());
return NewLoc;
@ -771,6 +771,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer,
const MCSymbol *lsda,
unsigned lsdaEncoding) {
MCContext &context = streamer.getContext();
const MCRegisterInfo &MRI = context.getRegisterInfo();
const TargetAsmInfo &TAI = context.getTargetAsmInfo();
bool verboseAsm = streamer.isVerboseAsm();
@ -824,7 +825,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer,
// Return Address Register
if (verboseAsm) streamer.AddComment("CIE Return Address Column");
streamer.EmitULEB128IntValue(TAI.getDwarfRARegNum(true));
streamer.EmitULEB128IntValue(MRI.getDwarfRegNum(MRI.getRARegister(), true));
// Augmentation Data Length (optional)
@ -870,9 +871,9 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer,
for (int i = 0, n = Moves.size(); i != n; ++i) {
MCSymbol *Label = Moves[i].getLabel();
const MachineLocation &Dst =
TranslateMachineLocation(TAI, Moves[i].getDestination());
TranslateMachineLocation(MRI, Moves[i].getDestination());
const MachineLocation &Src =
TranslateMachineLocation(TAI, Moves[i].getSource());
TranslateMachineLocation(MRI, Moves[i].getSource());
MCCFIInstruction Inst(Label, Dst, Src);
Instructions.push_back(Inst);
}

2
lib/MC/MCParser/AsmParser.cpp
View File

@ -2416,7 +2416,7 @@ bool GenericAsmParser::ParseRegisterOrRegisterNumber(int64_t &Register,
if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc,
DirectiveLoc))
return true;
Register = getContext().getTargetAsmInfo().getDwarfRegNum(RegNo, true);
Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true);
} else
return getParser().ParseAbsoluteExpression(Register);

11
lib/MC/MCParser/COFFAsmParser.cpp
View File

@ -12,10 +12,10 @@
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Support/COFF.h"
using namespace llvm;
@ -401,12 +401,16 @@ bool COFFAsmParser::ParseAtUnwindOrAtExcept(bool &unwind, bool &except) {
bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) {
SMLoc startLoc = getLexer().getLoc();
if (getLexer().is(AsmToken::Percent)) {
const TargetAsmInfo &TAI = getContext().getTargetAsmInfo();
const MCRegisterInfo &MRI = getContext().getRegisterInfo();
SMLoc endLoc;
unsigned LLVMRegNo;
if (getParser().getTargetParser().ParseRegister(LLVMRegNo,startLoc,endLoc))
return true;
#if 0
// FIXME: TargetAsmInfo::getCalleeSavedRegs() commits a serious layering
// violation so this validation code is disabled.
// Check that this is a non-volatile register.
const unsigned *NVRegs = TAI.getCalleeSavedRegs();
unsigned i;
@ -415,8 +419,9 @@ bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) {
break;
if (NVRegs[i] == 0)
return Error(startLoc, "expected non-volatile register");
#endif
int SEHRegNo = TAI.getSEHRegNum(LLVMRegNo);
int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo);
if (SEHRegNo < 0)
return Error(startLoc,"register can't be represented in SEH unwind info");
RegNo = SEHRegNo;

14
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -57,7 +57,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti)
: ARMGenRegisterInfo(), TII(tii), STI(sti),
: ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
BasePtr(ARM::R6) {
}
@ -649,10 +649,6 @@ cannotEliminateFrame(const MachineFunction &MF) const {
|| needsStackRealignment(MF);
}
unsigned ARMBaseRegisterInfo::getRARegister() const {
return ARM::LR;
}
unsigned
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -672,14 +668,6 @@ unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
return 0;
}
int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
const MachineFunction &MF) const {
switch (Reg) {

4
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -164,7 +164,6 @@ public:
bool cannotEliminateFrame(const MachineFunction &MF) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getBaseRegister() const { return BasePtr; }
@ -172,9 +171,6 @@ public:
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
bool isLowRegister(unsigned Reg) const;

6
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -117,13 +117,13 @@ extern "C" void LLVMInitializeARMMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
}
static MCRegisterInfo *createARMMCRegisterInfo() {
static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
MCRegisterInfo *X = new MCRegisterInfo();
InitARMMCRegisterInfo(X);
InitARMMCRegisterInfo(X, ARM::LR);
return X;
}
extern "C" void LLVMInitializeARMMCRegInfo() {
extern "C" void LLVMInitializeARMMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
}

17
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -40,8 +40,7 @@
using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
: AlphaGenRegisterInfo(),
TII(tii) {
: AlphaGenRegisterInfo(Alpha::R26), TII(tii) {
}
static long getUpper16(long l) {
@ -178,10 +177,6 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
}
unsigned AlphaRegisterInfo::getRARegister() const {
return Alpha::R26;
}
unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -198,16 +193,6 @@ unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
return 0;
}
int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}
int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
{
std::string s(AlphaRegDesc[reg].Name);

4
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -42,16 +42,12 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
int SPAdj, RegScavenger *RS = NULL) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
static std::string getPrettyName(unsigned reg);
};

10
lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp
View File

@ -40,6 +40,16 @@ extern "C" void LLVMInitializeAlphaMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
}
static MCRegisterInfo *createAlphaMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitAlphaMCRegisterInfo(X, Alpha::R26);
return X;
}
extern "C" void LLVMInitializeAlphaMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheAlphaTarget, createAlphaMCRegisterInfo);
}
static MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

17
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -37,7 +37,7 @@ using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
const TargetInstrInfo &tii)
: BlackfinGenRegisterInfo(), Subtarget(st), TII(tii) {}
: BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {}
const unsigned*
BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
@ -327,10 +327,6 @@ BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
}
unsigned BlackfinRegisterInfo::getRARegister() const {
return BF::RETS;
}
unsigned
BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -347,14 +343,3 @@ unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}
int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}

4
lib/Target/Blackfin/BlackfinRegisterInfo.h
View File

@ -53,15 +53,11 @@ namespace llvm {
int SPAdj, RegScavenger *RS = NULL) const;
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getRARegister() const;
// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
// Utility functions
void adjustRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,

10
lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp
View File

@ -41,6 +41,16 @@ extern "C" void LLVMInitializeBlackfinMCInstrInfo() {
createBlackfinMCInstrInfo);
}
static MCRegisterInfo *createBlackfinMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitBlackfinMCRegisterInfo(X, BF::RETS);
return X;
}
extern "C" void LLVMInitializeBlackfinMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheBlackfinTarget,
createBlackfinMCRegisterInfo);
}
static MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT,
StringRef CPU,

10
lib/Target/CBackend/CBackend.cpp
View File

@ -37,6 +37,7 @@
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
@ -64,6 +65,8 @@ extern "C" void LLVMInitializeCBackendTarget() {
extern "C" void LLVMInitializeCBackendMCAsmInfo() {}
extern "C" void LLVMInitializeCBackendMCRegisterInfo() {}
extern "C" void LLVMInitializeCBackendMCInstrInfo() {}
extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {}
@ -86,6 +89,7 @@ namespace {
LoopInfo *LI;
const Module *TheModule;
const MCAsmInfo* TAsm;
const MCRegisterInfo *MRI;
MCContext *TCtx;
const TargetData* TD;
@ -105,7 +109,7 @@ namespace {
static char ID;
explicit CWriter(formatted_raw_ostream &o)
: FunctionPass(ID), Out(o), IL(0), Mang(0), LI(0),
TheModule(0), TAsm(0), TCtx(0), TD(0), OpaqueCounter(0),
TheModule(0), TAsm(0), MRI(0), TCtx(0), TD(0), OpaqueCounter(0),
NextAnonValueNumber(0) {
initializeLoopInfoPass(*PassRegistry::getPassRegistry());
FPCounter = 0;
@ -145,6 +149,7 @@ namespace {
delete Mang;
delete TCtx;
delete TAsm;
delete MRI;
FPConstantMap.clear();
ByValParams.clear();
intrinsicPrototypesAlreadyGenerated.clear();
@ -1665,7 +1670,8 @@ bool CWriter::doInitialization(Module &M) {
TAsm = Match->createMCAsmInfo(Triple);
#endif
TAsm = new CBEMCAsmInfo();
TCtx = new MCContext(*TAsm, NULL);
MRI = new MCRegisterInfo();
TCtx = new MCContext(*TAsm, *MRI, NULL);
Mang = new Mangler(*TCtx, *TD);
// Keep track of which functions are static ctors/dtors so they can have

11
lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
View File

@ -39,6 +39,17 @@ extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
}
static MCRegisterInfo *createCellSPUMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitSPUMCRegisterInfo(X, SPU::R0);
return X;
}
extern "C" void LLVMInitializeCellSPUMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheCellSPUTarget,
createCellSPUMCRegisterInfo);
}
static MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

18
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -187,7 +187,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
const TargetInstrInfo &tii) :
SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii)
SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
{
}
@ -310,28 +310,12 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
}
}
unsigned
SPURegisterInfo::getRARegister() const
{
return SPU::R0;
}
unsigned
SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
{
return SPU::R1;
}
int
SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
}
int
SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
{

6
lib/Target/CellSPU/SPURegisterInfo.h
View File

@ -74,8 +74,6 @@ namespace llvm {
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
RegScavenger *RS = NULL) const;
//! Get return address register (LR, aka R0)
unsigned getRARegister() const;
//! Get the stack frame register (SP, aka R1)
unsigned getFrameRegister(const MachineFunction &MF) const;
@ -83,10 +81,6 @@ namespace llvm {
// New methods added:
//------------------------------------------------------------------------
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
//! Convert D-form load/store to X-form load/store
/*!
Converts a regiser displacement load/store into a register-indexed

10
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -79,13 +79,11 @@ extern "C" void LLVMInitializeCppBackendTarget() {
extern "C" void LLVMInitializeCppBackendMCAsmInfo() {}
extern "C" void LLVMInitializeCppBackendMCInstrInfo() {
RegisterMCInstrInfo<MCInstrInfo> X(TheCppBackendTarget);
}
extern "C" void LLVMInitializeCppBackendMCRegisterInfo() {}
extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {
RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCppBackendTarget);
}
extern "C" void LLVMInitializeCppBackendMCInstrInfo() {}
extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {}
namespace {
typedef std::vector<Type*> TypeList;

14
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -44,7 +44,7 @@ using namespace llvm;
MBlazeRegisterInfo::
MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
: MBlazeGenRegisterInfo(), Subtarget(ST), TII(tii) {}
: MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
@ -334,10 +334,6 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
MFI->setObjectOffset(MBlazeFI->getGPFI(), MBlazeFI->getGPStackOffset());
}
unsigned MBlazeRegisterInfo::getRARegister() const {
return MBlaze::R15;
}
unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -353,11 +349,3 @@ unsigned MBlazeRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0);
}
int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}

4
lib/Target/MBlaze/MBlazeRegisterInfo.h
View File

@ -69,15 +69,11 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
/// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
/// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

11
lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
View File

@ -40,6 +40,17 @@ extern "C" void LLVMInitializeMBlazeMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
}
static MCRegisterInfo *createMBlazeMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitMBlazeMCRegisterInfo(X, MBlaze::R15);
return X;
}
extern "C" void LLVMInitializeMBlazeMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheMBlazeTarget,
createMBlazeMCRegisterInfo);
}
static MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

12
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -29,7 +29,6 @@
using namespace llvm;
static MCInstrInfo *createMSP430MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMSP430MCInstrInfo(X);
@ -41,6 +40,17 @@ extern "C" void LLVMInitializeMSP430MCInstrInfo() {
}
static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitMSP430MCRegisterInfo(X, MSP430::PCW);
return X;
}
extern "C" void LLVMInitializeMSP430MCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheMSP430Target,
createMSP430MCRegisterInfo);
}
static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

16
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -34,7 +34,7 @@ using namespace llvm;
// FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(), TM(tm), TII(tii) {
: MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
StackAlign = TM.getFrameLowering()->getStackAlignment();
}
@ -233,22 +233,8 @@ MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
}
}
unsigned MSP430RegisterInfo::getRARegister() const {
return MSP430::PCW;
}
unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
}
int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("Not implemented yet!");
return 0;
}
int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("Not implemented yet!");
return 0;
}

5
lib/Target/MSP430/MSP430RegisterInfo.h
View File

@ -58,12 +58,7 @@ public:
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

10
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -39,6 +39,16 @@ extern "C" void LLVMInitializeMipsMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
}
static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitMipsMCRegisterInfo(X, Mips::RA);
return X;
}
extern "C" void LLVMInitializeMipsMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
}
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {

16
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -44,7 +44,7 @@ using namespace llvm;
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
const TargetInstrInfo &tii)
: MipsGenRegisterInfo(), Subtarget(ST), TII(tii) {}
: MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// Mips::RA, return the number that it corresponds to (e.g. 31).
@ -244,11 +244,6 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
MI.getOperand(i+1).ChangeToImmediate(Offset);
}
unsigned MipsRegisterInfo::
getRARegister() const {
return Mips::RA;
}
unsigned MipsRegisterInfo::
getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -267,12 +262,3 @@ getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
int MipsRegisterInfo::
getDwarfRegNum(unsigned RegNum, bool isEH) const {
return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}

4
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -57,15 +57,11 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
/// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
/// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

12
lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
View File

@ -40,6 +40,18 @@ extern "C" void LLVMInitializePTXMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
}
static MCRegisterInfo *createPTXMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
// PTX does not have a return address register.
InitPTXMCRegisterInfo(X, 0);
return X;
}
extern "C" void LLVMInitializePTXMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(ThePTX32Target, createPTXMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(ThePTX64Target, createPTXMCRegisterInfo);
}
static MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

3
lib/Target/PTX/PTXRegisterInfo.cpp
View File

@ -24,7 +24,8 @@ using namespace llvm;
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII)
: PTXGenRegisterInfo() {
// PTX does not have a return address register.
: PTXGenRegisterInfo(0) {
}
void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

12
lib/Target/PTX/PTXRegisterInfo.h
View File

@ -47,18 +47,6 @@ struct PTXRegisterInfo : public PTXGenRegisterInfo {
llvm_unreachable("PTX does not have a frame register");
return 0;
}
virtual unsigned getRARegister() const {
llvm_unreachable("PTX does not have a return address register");
return 0;
}
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const {
return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const {
return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
}
}; // struct PTXRegisterInfo
} // namespace llvm

15
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -40,6 +40,21 @@ extern "C" void LLVMInitializePowerPCMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
}
static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
Triple TheTriple(TT);
bool isPPC64 = (TheTriple.getArch() == Triple::ppc64);
unsigned Flavour = isPPC64 ? 0 : 1;
unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
MCRegisterInfo *X = new MCRegisterInfo();
InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
return X;
}
extern "C" void LLVMInitializePowerPCMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(ThePPC32Target, createPPCMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(ThePPC64Target, createPPCMCRegisterInfo);
}
static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {

33
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -113,7 +113,10 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
const TargetInstrInfo &tii)
: PPCGenRegisterInfo(), Subtarget(ST), TII(tii) {
: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
ST.isPPC64() ? 0 : 1,
ST.isPPC64() ? 0 : 1),
Subtarget(ST), TII(tii) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
@ -668,10 +671,6 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
}
unsigned PPCRegisterInfo::getRARegister() const {
return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
}
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
@ -688,27 +687,3 @@ unsigned PPCRegisterInfo::getEHExceptionRegister() const {
unsigned PPCRegisterInfo::getEHHandlerRegister() const {
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
}
/// DWARFFlavour - Flavour of dwarf regnumbers
///
namespace DWARFFlavour {
enum {
PPC64 = 0, PPC32 = 1
};
}
int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
unsigned Flavour = Subtarget.isPPC64() ?
DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
}
int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
unsigned Flavour = Subtarget.isPPC64() ?
DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
}

4
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -62,15 +62,11 @@ public:
int SPAdj, RegScavenger *RS = NULL) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

10
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -39,6 +39,16 @@ extern "C" void LLVMInitializeSparcMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
}
static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitSparcMCRegisterInfo(X, SP::I7);
return X;
}
extern "C" void LLVMInitializeSparcMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo);
}
static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

14
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -31,7 +31,7 @@ using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(), Subtarget(st), TII(tii) {
: SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
}
const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
@ -113,10 +113,6 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
void SparcRegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
unsigned SparcRegisterInfo::getRARegister() const {
return SP::I7;
}
unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return SP::I6;
}
@ -130,11 +126,3 @@ unsigned SparcRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}

4
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -46,15 +46,11 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

11
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -40,6 +40,17 @@ extern "C" void LLVMInitializeSystemZMCInstrInfo() {
createSystemZMCInstrInfo);
}
static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitSystemZMCRegisterInfo(X, 0);
return X;
}
extern "C" void LLVMInitializeSystemZMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheSystemZTarget,
createSystemZMCRegisterInfo);
}
static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT,
StringRef CPU,
StringRef FS) {

17
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -33,7 +33,7 @@ using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
const SystemZInstrInfo &tii)
: SystemZGenRegisterInfo(), TM(tm), TII(tii) {
: SystemZGenRegisterInfo(0), TM(tm), TII(tii) {
}
const unsigned*
@ -126,11 +126,6 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(i+1).ChangeToImmediate(Offset);
}
unsigned SystemZRegisterInfo::getRARegister() const {
assert(0 && "What is the return address register");
return 0;
}
unsigned
SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
assert(0 && "What is the frame register");
@ -146,13 +141,3 @@ unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
assert(0 && "What is the exception handler register");
return 0;
}
int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}

4
lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -48,15 +48,11 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
int SPAdj, RegScavenger *RS = NULL) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

1
lib/Target/TargetAsmInfo.cpp
View File

@ -18,6 +18,5 @@ using namespace llvm;
TargetAsmInfo::TargetAsmInfo(const TargetMachine &TM) {
TLOF = &TM.getTargetLowering()->getObjFileLowering();
TFI = TM.getFrameLowering();
TRI = TM.getRegisterInfo();
TFI->getInitialFrameState(InitialFrameState);
}

143
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -107,6 +107,135 @@ void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
}
}
unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::x86_64)
return DWARFFlavour::X86_64;
if (TheTriple.isOSDarwin())
return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
if (TheTriple.getOS() == Triple::MinGW32 ||
TheTriple.getOS() == Triple::Cygwin)
// Unsupported by now, just quick fallback
return DWARFFlavour::X86_32_Generic;
return DWARFFlavour::X86_32_Generic;
}
/// getX86RegNum - This function maps LLVM register identifiers to their X86
/// specific numbering, which is used in various places encoding instructions.
unsigned X86_MC::getX86RegNum(unsigned RegNo) {
switch(RegNo) {
case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
return N86::ESP;
case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
return N86::EBP;
case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
return N86::ESI;
case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
return N86::EDI;
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
return N86::EAX;
case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
return N86::ECX;
case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
return N86::EDX;
case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
return N86::EBX;
case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
return N86::ESP;
case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
return N86::EBP;
case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
return N86::ESI;
case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
return N86::EDI;
case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
return RegNo-X86::ST0;
case X86::XMM0: case X86::XMM8:
case X86::YMM0: case X86::YMM8: case X86::MM0:
return 0;
case X86::XMM1: case X86::XMM9:
case X86::YMM1: case X86::YMM9: case X86::MM1:
return 1;
case X86::XMM2: case X86::XMM10:
case X86::YMM2: case X86::YMM10: case X86::MM2:
return 2;
case X86::XMM3: case X86::XMM11:
case X86::YMM3: case X86::YMM11: case X86::MM3:
return 3;
case X86::XMM4: case X86::XMM12:
case X86::YMM4: case X86::YMM12: case X86::MM4:
return 4;
case X86::XMM5: case X86::XMM13:
case X86::YMM5: case X86::YMM13: case X86::MM5:
return 5;
case X86::XMM6: case X86::XMM14:
case X86::YMM6: case X86::YMM14: case X86::MM6:
return 6;
case X86::XMM7: case X86::XMM15:
case X86::YMM7: case X86::YMM15: case X86::MM7:
return 7;
case X86::ES: return 0;
case X86::CS: return 1;
case X86::SS: return 2;
case X86::DS: return 3;
case X86::FS: return 4;
case X86::GS: return 5;
case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
case X86::CR2: case X86::CR10: case X86::DR2: return 2;
case X86::CR3: case X86::CR11: case X86::DR3: return 3;
case X86::CR4: case X86::CR12: case X86::DR4: return 4;
case X86::CR5: case X86::CR13: case X86::DR5: return 5;
case X86::CR6: case X86::CR14: case X86::DR6: return 6;
case X86::CR7: case X86::CR15: case X86::DR7: return 7;
// Pseudo index registers are equivalent to a "none"
// scaled index (See Intel Manual 2A, table 2-3)
case X86::EIZ:
case X86::RIZ:
return 4;
default:
assert((int(RegNo) > 0) && "Unknown physical register!");
return 0;
}
}
void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
// FIXME: TableGen these.
for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
int SEH = X86_MC::getX86RegNum(Reg);
switch (Reg) {
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
SEH += 8;
break;
}
MRI->mapLLVMRegToSEHReg(Reg, SEH);
}
}
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT);
@ -150,13 +279,21 @@ extern "C" void LLVMInitializeX86MCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
}
static MCRegisterInfo *createX86MCRegisterInfo() {
static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
Triple TheTriple(TT);
unsigned RA = (TheTriple.getArch() == Triple::x86_64)
? X86::RIP // Should have dwarf #16.
: X86::EIP; // Should have dwarf #8.
MCRegisterInfo *X = new MCRegisterInfo();
InitX86MCRegisterInfo(X);
InitX86MCRegisterInfo(X, RA,
X86_MC::getDwarfRegFlavour(TT, false),
X86_MC::getDwarfRegFlavour(TT, true));
X86_MC::InitLLVM2SEHRegisterMapping(X);
return X;
}
extern "C" void LLVMInitializeX86MCRegInfo() {
extern "C" void LLVMInitializeX86MCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
}

25
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -17,12 +17,29 @@
#include <string>
namespace llvm {
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheX86_32Target, TheX86_64Target;
/// DWARFFlavour - Flavour of dwarf regnumbers
///
namespace DWARFFlavour {
enum {
X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
};
}
/// N86 namespace - Native X86 register numbers
///
namespace N86 {
enum {
EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
};
}
namespace X86_MC {
std::string ParseX86Triple(StringRef TT);
@ -33,7 +50,13 @@ namespace X86_MC {
void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
/// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
unsigned getX86RegNum(unsigned RegNo);
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
/// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
/// This is exposed so Asm parser, etc. do not need to go through
/// TargetRegistry.
MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,

32
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -98,8 +98,6 @@ namespace {
void emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField,
intptr_t PCAdj = 0);
unsigned getX86RegNum(unsigned RegNo) const;
};
template<class CodeEmitter>
@ -346,11 +344,6 @@ void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
MCE.emitWordLE(0);
}
template<class CodeEmitter>
unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
return X86RegisterInfo::getX86RegNum(RegNo);
}
inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
unsigned RM) {
assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
@ -360,7 +353,7 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
unsigned RegOpcodeFld){
MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
}
template<class CodeEmitter>
@ -498,7 +491,7 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
// 2-7) and absolute references.
unsigned BaseRegNo = -1U;
if (BaseReg != 0 && BaseReg != X86::RIP)
BaseRegNo = getX86RegNum(BaseReg);
BaseRegNo = X86_MC::getX86RegNum(BaseReg);
if (// The SIB byte must be used if there is an index register.
IndexReg.getReg() == 0 &&
@ -574,15 +567,15 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
// Manual 2A, table 2-7. The displacement has already been output.
unsigned IndexRegNo;
if (IndexReg.getReg())
IndexRegNo = getX86RegNum(IndexReg.getReg());
IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
IndexRegNo = 4;
emitSIBByte(SS, IndexRegNo, 5);
} else {
unsigned BaseRegNo = getX86RegNum(BaseReg);
unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
unsigned IndexRegNo;
if (IndexReg.getReg())
IndexRegNo = getX86RegNum(IndexReg.getReg());
IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
else
IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
emitSIBByte(SS, IndexRegNo, BaseRegNo);
@ -809,7 +802,8 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
}
case X86II::AddRegFrm: {
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
MCE.emitByte(BaseOpcode +
X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
if (CurOp == NumOps)
break;
@ -844,7 +838,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRMDestReg: {
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(),
@ -854,7 +848,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRMDestMem: {
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp,
getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
.getReg()));
CurOp += X86::AddrNumOperands + 1;
if (CurOp != NumOps)
@ -866,7 +860,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRMSrcReg:
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
getX86RegNum(MI.getOperand(CurOp).getReg()));
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
CurOp += 2;
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(),
@ -880,8 +874,8 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
X86II::getSizeOfImm(Desc->TSFlags) : 0;
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
PCAdj);
emitMemModRMByte(MI, CurOp+1,
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
CurOp += AddrOperands + 1;
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(),
@ -968,7 +962,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
MCE.emitByte(BaseOpcode);
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
getX86RegNum(MI.getOperand(CurOp).getReg()));
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
++CurOp;
break;

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -8552,8 +8552,8 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
@ -8657,7 +8657,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
// This is storing the opcode for MOV32ri.
const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
OutChains[0] = DAG.getStore(Root, dl,
DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Trmp, MachinePointerInfo(TrmpAddr),

2
lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -45,7 +45,7 @@ public:
}
static unsigned GetX86RegNum(const MCOperand &MO) {
return X86RegisterInfo::getX86RegNum(MO.getReg());
return X86_MC::getX86RegNum(MO.getReg());
}
// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range

141
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -53,7 +53,13 @@ ForceStackAlign("force-align-stack",
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const TargetInstrInfo &tii)
: X86GenRegisterInfo(), TM(tm), TII(tii) {
: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
? X86::RIP : X86::EIP,
X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
TM(tm), TII(tii) {
X86_MC::InitLLVM2SEHRegisterMapping(this);
// Cache some information.
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
Is64Bit = Subtarget->is64Bit();
@ -70,40 +76,6 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
}
}
static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
if (!Subtarget->is64Bit()) {
if (Subtarget->isTargetDarwin()) {
if (isEH)
return DWARFFlavour::X86_32_DarwinEH;
else
return DWARFFlavour::X86_32_Generic;
} else if (Subtarget->isTargetCygMing()) {
// Unsupported by now, just quick fallback
return DWARFFlavour::X86_32_Generic;
} else {
return DWARFFlavour::X86_32_Generic;
}
}
return DWARFFlavour::X86_64;
}
/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
/// specific numbering, used in debug info and exception tables.
int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = getFlavour(Subtarget, isEH);
return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
}
/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = getFlavour(Subtarget, isEH);
return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
}
/// getCompactUnwindRegNum - This function maps the register to the number for
/// compact unwind encoding. Return -1 if the register isn't valid.
int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
@ -121,7 +93,7 @@ int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
int
X86RegisterInfo::getSEHRegNum(unsigned i) const {
int reg = getX86RegNum(i);
int reg = X86_MC::getX86RegNum(i);
switch (i) {
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
@ -140,98 +112,6 @@ X86RegisterInfo::getSEHRegNum(unsigned i) const {
return reg;
}
/// getX86RegNum - This function maps LLVM register identifiers to their X86
/// specific numbering, which is used in various places encoding instructions.
unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
switch(RegNo) {
case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
return N86::ESP;
case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
return N86::EBP;
case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
return N86::ESI;
case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
return N86::EDI;
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
return N86::EAX;
case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
return N86::ECX;
case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
return N86::EDX;
case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
return N86::EBX;
case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
return N86::ESP;
case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
return N86::EBP;
case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
return N86::ESI;
case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
return N86::EDI;
case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
return RegNo-X86::ST0;
case X86::XMM0: case X86::XMM8:
case X86::YMM0: case X86::YMM8: case X86::MM0:
return 0;
case X86::XMM1: case X86::XMM9:
case X86::YMM1: case X86::YMM9: case X86::MM1:
return 1;
case X86::XMM2: case X86::XMM10:
case X86::YMM2: case X86::YMM10: case X86::MM2:
return 2;
case X86::XMM3: case X86::XMM11:
case X86::YMM3: case X86::YMM11: case X86::MM3:
return 3;
case X86::XMM4: case X86::XMM12:
case X86::YMM4: case X86::YMM12: case X86::MM4:
return 4;
case X86::XMM5: case X86::XMM13:
case X86::YMM5: case X86::YMM13: case X86::MM5:
return 5;
case X86::XMM6: case X86::XMM14:
case X86::YMM6: case X86::YMM14: case X86::MM6:
return 6;
case X86::XMM7: case X86::XMM15:
case X86::YMM7: case X86::YMM15: case X86::MM7:
return 7;
case X86::ES: return 0;
case X86::CS: return 1;
case X86::SS: return 2;
case X86::DS: return 3;
case X86::FS: return 4;
case X86::GS: return 5;
case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
case X86::CR2: case X86::CR10: case X86::DR2: return 2;
case X86::CR3: case X86::CR11: case X86::DR3: return 3;
case X86::CR4: case X86::CR12: case X86::DR4: return 4;
case X86::CR5: case X86::CR13: case X86::DR5: return 5;
case X86::CR6: case X86::CR14: case X86::DR6: return 6;
case X86::CR7: case X86::CR15: case X86::DR7: return 7;
// Pseudo index registers are equivalent to a "none"
// scaled index (See Intel Manual 2A, table 2-3)
case X86::EIZ:
case X86::RIZ:
return 4;
default:
assert(isVirtualRegister(RegNo) && "Unknown physical register!");
llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
return 0;
}
}
const TargetRegisterClass *
X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B,
@ -741,11 +621,6 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
}
unsigned X86RegisterInfo::getRARegister() const {
return Is64Bit ? X86::RIP // Should have dwarf #16.
: X86::EIP; // Should have dwarf #8.
}
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? FramePtr : StackPtr;

22
lib/Target/X86/X86RegisterInfo.h
View File

@ -24,22 +24,6 @@ namespace llvm {
class TargetInstrInfo;
class X86TargetMachine;
/// N86 namespace - Native X86 register numbers
///
namespace N86 {
enum {
EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
};
}
/// DWARFFlavour - Flavour of dwarf regnumbers
///
namespace DWARFFlavour {
enum {
X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
};
}
class X86RegisterInfo : public X86GenRegisterInfo {
public:
X86TargetMachine &TM;
@ -73,11 +57,6 @@ public:
/// register identifier.
static unsigned getX86RegNum(unsigned RegNo);
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
/// (created by TableGen) for target dependencies.
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
// FIXME: This should be tablegen'd like getDwarfRegNum is
int getSEHRegNum(unsigned i) const;
@ -136,7 +115,6 @@ public:
int SPAdj, RegScavenger *RS = NULL) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getStackRegister() const { return StackPtr; }
// FIXME: Move to FrameInfok

10
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -39,6 +39,16 @@ extern "C" void LLVMInitializeXCoreMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
}
static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitXCoreMCRegisterInfo(X, XCore::LR);
return X;
}
extern "C" void LLVMInitializeXCoreMCRegisterInfo() {
TargetRegistry::RegisterMCRegInfo(TheXCoreTarget, createXCoreMCRegisterInfo);
}
static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();

14
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -39,7 +39,7 @@
using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
: XCoreGenRegisterInfo(), TII(tii) {
: XCoreGenRegisterInfo(XCore::LR), TII(tii) {
}
// helper functions
@ -321,20 +321,8 @@ loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
}
int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
}
unsigned XCoreRegisterInfo::getRARegister() const {
return XCore::LR;
}

5
lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -60,7 +60,6 @@ public:
int SPAdj, RegScavenger *RS = NULL) const;
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
//! Return the array of argument passing registers
@ -74,10 +73,6 @@ public:
//! Return whether to emit frame moves
static bool needsFrameMoves(const MachineFunction &MF);
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

6
tools/llvm-mc/llvm-mc.cpp
View File

@ -309,6 +309,9 @@ static int AssembleInput(const char *ProgName) {
llvm::OwningPtr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(TripleName));
assert(MAI && "Unable to create target asm info!");
llvm::OwningPtr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
assert(MRI && "Unable to create target register info!");
// Package up features to be passed to target/subtarget
std::string FeaturesStr;
@ -327,7 +330,7 @@ static int AssembleInput(const char *ProgName) {
}
const TargetAsmInfo *tai = new TargetAsmInfo(*TM);
MCContext Ctx(*MAI, tai);
MCContext Ctx(*MAI, *MRI, tai);
if (SaveTempLabels)
Ctx.setAllowTemporaryLabels(false);
@ -438,6 +441,7 @@ int main(int argc, char **argv) {
llvm::InitializeAllTargets();
llvm::InitializeAllMCAsmInfos();
llvm::InitializeAllMCInstrInfos();
llvm::InitializeAllMCRegisterInfos();
llvm::InitializeAllMCSubtargetInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();

5
tools/lto/LTOCodeGenerator.cpp
View File

@ -31,6 +31,7 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetSelect.h"
#include "llvm/Support/CommandLine.h"
@ -74,6 +75,7 @@ LTOCodeGenerator::LTOCodeGenerator()
{
InitializeAllTargets();
InitializeAllMCAsmInfos();
InitializeAllMCRegisterInfos();
InitializeAllMCSubtargetInfos();
InitializeAllAsmPrinters();
}
@ -308,7 +310,8 @@ void LTOCodeGenerator::applyScopeRestrictions() {
passes.add(createVerifierPass());
// mark which symbols can not be internalized
MCContext Context(*_target->getMCAsmInfo(), NULL);
MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),
NULL);
Mangler mangler(Context, *_target->getTargetData());
std::vector<const char*> mustPreserveList;
SmallPtrSet<GlobalValue*, 8> asmUsed;

4
tools/lto/LTOModule.cpp
View File

@ -40,6 +40,7 @@
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetSelect.h"
@ -662,7 +663,8 @@ static bool isAliasToDeclaration(const GlobalAlias &V) {
bool LTOModule::ParseSymbols() {
// Use mangler to add GlobalPrefix to names to match linker names.
MCContext Context(*_target->getMCAsmInfo(), NULL);
MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),
NULL);
Mangler mangler(Context, *_target->getTargetData());
// add functions

223
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -91,6 +91,117 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS,
OS << "#endif // GET_REGINFO_ENUM\n\n";
}
void
RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
const std::vector<CodeGenRegister*> &Regs,
bool isCtor) {
// Collect all information about dwarf register numbers
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
// First, just pull all provided information to the map
unsigned maxLength = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
<< "specified multiple times\n";
DwarfRegNums[Reg] = RegNums;
}
if (!maxLength)
return;
// Now we know maximal length of number list. Append -1's, where needed
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
// Emit reverse information about the dwarf register numbers.
for (unsigned j = 0; j < 2; ++j) {
OS << " switch (";
if (j == 0)
OS << "DwarfFlavour";
else
OS << "EHFlavour";
OS << ") {\n"
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " break;\n";
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n";
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int DwarfRegNo = I->second[i];
if (DwarfRegNo < 0)
continue;
OS << " ";
if (!isCtor)
OS << "RI->";
OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
<< getQualifiedName(I->first) << ", ";
if (j == 0)
OS << "false";
else
OS << "true";
OS << " );\n";
}
OS << " break;\n";
}
OS << " }\n";
}
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");
if (!V || !V->getValue())
continue;
DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
Record *Alias = DI->getDef();
DwarfRegNums[Reg] = DwarfRegNums[Alias];
}
// Emit information about the dwarf register numbers.
for (unsigned j = 0; j < 2; ++j) {
OS << " switch (";
if (j == 0)
OS << "DwarfFlavour";
else
OS << "EHFlavour";
OS << ") {\n"
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " break;\n";
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n";
// Sort by name to get a stable order.
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
OS << " ";
if (!isCtor)
OS << "RI->";
OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
<< RegNo << ", ";
if (j == 0)
OS << "false";
else
OS << "true";
OS << " );\n";
}
OS << " break;\n";
}
OS << " }\n";
}
}
//
// runMCDesc - Print out MC register descriptions.
//
@ -188,9 +299,15 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n}\n\n";
<< Regs.size()+1 << ", RA);\n\n";
EmitRegMapping(OS, Regs, false);
OS << "}\n\n";
OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
@ -213,12 +330,8 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
OS << "namespace llvm {\n\n";
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName << "();\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
<< " explicit " << ClassName
<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n"
<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
@ -662,102 +775,16 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << ClassName << "::" << ClassName
<< "()\n"
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " " << TargetName << "SubRegIndexTable) {\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n"
<< "}\n\n";
<< Regs.size()+1 << ", RA);\n\n";
// Collect all information about dwarf register numbers
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
EmitRegMapping(OS, Regs, true);
// First, just pull all provided information to the map
unsigned maxLength = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
<< "specified multiple times\n";
DwarfRegNums[Reg] = RegNums;
}
// Now we know maximal length of number list. Append -1's, where needed
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
// Emit reverse information about the dwarf register numbers.
OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
<< "unsigned Flavour) const {\n"
<< " switch (Flavour) {\n"
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " return -1;\n";
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n"
<< " switch (DwarfRegNum) {\n"
<< " default:\n"
<< " assert(0 && \"Invalid DwarfRegNum\");\n"
<< " return -1;\n";
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int DwarfRegNo = I->second[i];
if (DwarfRegNo >= 0)
OS << " case " << DwarfRegNo << ":\n"
<< " return " << getQualifiedName(I->first) << ";\n";
}
OS << " };\n";
}
OS << " };\n}\n\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");
if (!V || !V->getValue())
continue;
DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
Record *Alias = DI->getDef();
DwarfRegNums[Reg] = DwarfRegNums[Alias];
}
// Emit information about the dwarf register numbers.
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const {\n"
<< " switch (Flavour) {\n"
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " return -1;\n";
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n"
<< " switch (RegNum) {\n"
<< " default:\n"
<< " assert(0 && \"Invalid RegNum\");\n"
<< " return -1;\n";
// Sort by name to get a stable order.
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
OS << " case " << getQualifiedName(I->first) << ":\n"
<< " return " << RegNo << ";\n";
}
OS << " };\n";
}
OS << " };\n}\n\n";
OS << "}\n\n";
OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";

6
utils/TableGen/RegisterInfoEmitter.h
View File

@ -17,10 +17,12 @@
#define REGISTER_INFO_EMITTER_H
#include "TableGenBackend.h"
#include <vector>
namespace llvm {
class CodeGenRegBank;
struct CodeGenRegister;
class CodeGenTarget;
class RegisterInfoEmitter : public TableGenBackend {
@ -44,6 +46,10 @@ public:
// run - Output the register file description.
void run(raw_ostream &o);
private:
void EmitRegMapping(raw_ostream &o,
const std::vector<CodeGenRegister*> &Regs, bool isCtor);
};
} // End llvm namespace